verilog 菜鸟问题 verilog, 菜鸟

chengkanghe

自己先顶一下。以下是我自己编的测试环境：
`timescale 1ns/1ns
`include "./byte_mult2.v"
module multest;
wire[7:0] out;
reg[3:0] nibble1,nibble2;
reg clk,reset;

multiply multiply(nibble1,nibble2,out,clk,reset);

always begin
clk= 0;
forever #50 clk = ~clk;
  end
initial
begin
  clk=0;
  reset=1;
  nibble1={$random}%16;
  nibble2={$random}%16;
#50 reset=0;
  end
  
  begin
      
# 100 nibble1 = {$random}%16;
      nibble2={$random}%16;
        
  end
multiply multiply(nibble1,nibble2,out,clk,reset);
endmodule
编译时老提示:
Error: E:/multiply/multiply.tst(25): near "#":  expecting: EVENT INTEGER REAL REALTIME REG TIME AUTOMATIC IDENT STRING
不知道为什么
25行为 # 100 nibble1 = {$random}%16;

chengkanghe

最近开始学verilog，下面是一个乘法器的源代码，我想写个模拟环境，其中有always语句。请问高人这种类似的程序怎么写模拟环境环境，谁以能对下面的乘法器，给我作个例子。 odule byte_mult2 (nibble1, nibble2, byte_out, clk, reset); input [3:0] nibble1, nibble2; input clk, reset; output byte_out; reg [7:0] byte_out, stored3, stored2, stored1, stored0; always @ (posedge clk or posedge reset) if (reset) begin byte_out <= 0; stored3 <= 0; stored2 <= 0; stored1 <= 0; stored0 <= 0; end else begin // Shift nibble by padding with zeroes. MSB must be zero to make // the size of the left-hand side match the set size of the // right-hand side. stored3 <= nibble1[3] ? {1'b0, nibble2[3:0], 3'b0} : 8'b0; stored2 <= nibble1[2] ? {2'b0, nibble2[3:0], 2'b0} : 8'b0; stored1 <= nibble1[1] ? {3'b0, nibble2[3:0], 3'b0} : 8'b0; stored0 <= nibble1[0] ? {4'b0, nibble2[3:0]} : 8'b0; byte_out <= stored3 + stored2 + stored1 + stored0; end endmodule

chengkanghe

编译成功了
可是怎么没波形呢，源码改成如下
`timescale 1ns/1ns
`include "./byte_mult2.v"
module multest;
wire[7:0] out;
reg[3:0] nibble1,nibble2;
reg clk,reset;

multiply multiply(nibble1,nibble2,out,clk,reset);


initial
begin
  clk=0;
  reset=1;
  nibble1={$random}%16;
  nibble2={$random}%16;
  end
always
  begin
    clk= 0;
forever #50 clk = ~clk;
#100   reset=2;
   nibble1 ={$random}%16;
   nibble2={$random}%16;
#400 $finish;
        
  end
//multiply multiply(nibble1,nibble2,out,clk,reset);
endmodule