求助:用verilog测试XilinxIP核中的除法器无法仿真 除法器, XilinxIP, verilog, 仿真, 求助

ksfblc

错误提示如下

# ** Error: (vsim-3033) Divider29_6_29.v(94): Instantiation of 'DIV_GEN_V1_0' failed. The design unit was not found.
# Region: /b_v/uut
# Searched libraries:
# E:\Xilinx91i\verilog\mti_se\XilinxCoreLib_ver
# E:\Xilinx91i\verilog\mti_se\unisims_ver
# work
# Loading work.glbl
# Error loading design

请问各位应该怎么处理啊?

[此贴子已经被作者于2008-5-28 21:04:41编辑过]

ksfblc

加了Testbench的