一段交织编码的verilog程序 verilog, 程序, 编码

godjohsn

一段实现16*12交织编码的verilog代码：
module interleaver(clk, reset, x, y);
input clk;
input reset;
input [15:0] x;
output [15:0] y;

reg [7:0] addra, addrb;
wire [7:0] addrat, addrbt;
reg [3:0] cnt,addr0;
always @(posedge clk) begin
if(!reset) begin
addra <= 0;
addrb <= 0;
cnt <= 0;
end
else begin
if(addra == 191)
addra <= 0;
else
addra <= addra + 1;
if (addrb > 175) begin
addrb <= addr0;
if(cnt == 11)
cnt <= 0;
else
cnt <= cnt + 1;
end
else begin
cnt <= cnt;
addrb <= addrb + 16;
end
end
end

always @(cnt) begin
case (cnt)
4'b0000: addr0 <= 0;
4'b0001: addr0 <= 1;
4'b0010: addr0 <= 2;
4'b0011: addr0 <= 3;
4'b0100: addr0 <= 4;
4'b0101: addr0 <= 5;
4'b0110: addr0 <= 6;
4'b0111: addr0 <= 7;
4'b1000: addr0 <= 8;
4'b1001: addr0 <= 9;
4'b1010: addr0 <= 10;
4'b1011: addr0 <= 11;
default: addr0 <= 0;
endcase
end

block_ram block_ram(
.addra(addra),
.addrb(addrb),
.clka(clk),
.clkb(clk),
.dina(x),
.doutb(y),
.wea(reset));

endmodule
其中block_ram是利用了ip核实现的双口ram
port a写入，port b读出，可是调用modelsim仿真发现输出全为未知状态？谁能帮忙给看看？ram的width a和width b应该设为多少？