求教，本人新学CPLD不久，用Verilog编写了一段Quartus II程 序，通过单片机和CPLD对继电器开关进行开合控制，CPLD选用 的是EPM7512AETC144-10。在仿真的时候，功能仿真出现错误， 时序仿真确是正确的，让我比较困惑。求教各位前辈高手指点 指点。
程序如下：
module zc(in,data,out,rst);
input data,rst;
input [1:0]in;
output [3:0]out;
reg [3:0]out,add,add1,latch;
always@(in or data or rst or latch )
begin
if(rst)
begin
add = 4'b1111;
add1 = 4'b1111;
latch= 4'b1111;
out = 4'b1111;
end
else
begin
if(!data)
begin
case(in)
2'b00:add=4'b1110;
2'b01:add=4'b1101;
2'b10:add=4'b1011;
2'b11:add=4'b0111;
endcase
add1=add&latch;
//latch=add1;
out[0]=add1 [0]?1'b1:1'b0;
out[1]=add1 [1]?1'b1:1'b0;
out[2]=add1 [2]?1'b1:1'b0;
out[3]=add1 [3]?1'b1:1'b0;
latch=out;
end
else
begin
case(in)
2'b00:begin add=4'b1110;end
2'b01:begin add=4'b1101;end
2'b10:begin add=4'b1011;end
2'b11:begin add=4'b0110;end
endcase
out[0]=add[0]? latch[0]:1'b1;
out[1]=add[1]? latch[1]:1'b1;
out[2]=add[2]? latch[2]:1'b1;
out[3]=add[3]? latch[3]:1'b1;
latch=out;
end
end
end
endmodule
我在综合编译的时候，出现2个警告：
Warning: Verilog HDL Always Construct warning at zc.v (8): variable add1 may not be assigned a new value in every possible path through the Always Construct. Variable add1 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at zc.v (8): variable latch may not be assigned a new value in every possible path through the Always Construct. Variable latch holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
敬请指教。 | 
