代码如下: library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tTV is
port (
clock_50 : in std_logic;
TD_DATA : in std_logic_vector(7 downto 0);
TD_HS,TD_VS : in std_logic;
LEDR : out std_logic_vector(11 downto 0);
HEX0 : out std_logic_vector(0 to 6);
HEX1 : out std_logic_vector(0 to 6);
HEX2 : out std_logic_vector(0 to 6);
HEX3 : out std_logic_vector(0 to 6);
HEX4 : out std_logic_vector(0 to 6);
HEX5 : out std_logic_vector(0 to 6);
HEX6 : out std_logic_vector(0 to 6);
HEX7 : out std_logic_vector(0 to 6));
end entity tTV; architecture one of tTV is
component char_7seg is
port( M : in std_logic_vector(3 downto 0);
D : out std_logic_vector(0 to 6));
end component char_7seg; signal h_count,v_count,rh,rv : std_logic_vector(11 downto 0);
begin
process(TD_HS)
begin
if clock_50='1' and clock_50'event then
if TD_HS='0' then
h_count<=h_count+1;
else h_count<=(others=>'0');
end if;
end if;
end process;
process(TD_HS)
begin
if TD_HS='1' and TD_HS'event then
rh<=h_count;
end if;
end process;
process(TD_VS)
begin
if clock_50='1' and clock_50'event then
if TD_VS='0' then
v_count<=v_count+1;
else v_count<=(others=>'0');
end if;
end if;
end process;
process(TD_VS)
begin
if TD_VS='1' and TD_VS'event then
rv<=v_count;
end if;
end process;
u1: char_7seg port map(rh(11 downto 8),HEX0);
u2: char_7seg port map(rh(7 downto 4),HEX1);
u3: char_7seg port map(rh(3 downto 0),HEX2);
u4: char_7seg port map(rv(11 downto 8),HEX3);
u5: char_7seg port map(rv(7 downto 4),HEX4);
u6: char_7seg port map(rv(3 downto 0),HEX5);
u7: char_7seg port map(TD_DATA(7 downto 4),HEX6);
u8: char_7seg port map(TD_DATA(3 downto 0),HEX7);
end architecture ;
library ieee;
use ieee.std_logic_1164.all;
entity char_7seg is
port( M : in std_logic_vector(3 downto 0);
D : out std_logic_vector(0 to 6));
end entity char_7seg; architecture one of char_7seg is
signal D0 : std_logic_vector(0 to 6);
begin
process(M)
begin
case M is
when "0000" => D0 <= "0000001";
when "0001" => D0 <= "1001111";
when "0010" => D0 <= "0010010";
when "0011" => D0 <= "0000110";
when "0100" => D0 <= "1001100";
when "0101" => D0 <= "0100100";
when "0110" => D0 <= "0100000";
when "0111" => D0 <= "0001111";
when "1000" => D0 <= "0000000";
when "1001" => D0 <= "0000100";
when "1010" => D0 <= "0001000";
when "1011" => D0 <= "1100000";
when "1100" => D0 <= "1110010";
when "1101" => D0 <= "1000010";
when "1110" => D0 <= "0110000";
when "1111" => D0 <= "0111000";
when others => D0 <= "1111111";
end case;
end process;
D <= D0;
end architecture; HEX0 ~HEX7:分别为0 0 0 0 0 0 8 8 请问是什么问题啊??代码有错吗? | 
