I manually add MIG2.1 generating verilog files to my project, and our FPGA is xc3sd1800a-4fg676, our pinout about ddr2 ( MT47h32M*16-37e) part are defined by ourself, completely independent from MIG core. So there are some questions:
1. I need modify the location definition part in ucf file based on MIG.ucf, for example, I define cntrl0_ddr2_dq[6] to pin A24, but there are some correponding RLOC, and slice, I dont know how to modify them. NET "cntrl0_ddr2_dq[6]" LOC = "U7"; //LOC U7 changed to A24
INST "main_00/top0/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit6" LOC = SLICE_X0Y36; //how to do correponding about slice location????
INST "main_00/top0/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit6" LOC = SLICE_X0Y37; 2. XIL_ROUTE_ENABLE_DATA_CAPTURE in ug086 P383, there is a paragraph For the data bits to be routed properly, the environment variable
XIL_ROUTE_ENABLE_DATA_CAPTURE must be enabled when PAR is run. This
environment variable is set in the implementation script file ise_flow.bat provided in
the /par MIG output directory. The user must set this environment variable when running
the design using the GUI mode from create_ise.bat. ( how to set the variable ??? )
thanks a million Jane | 
