为verilog文件建立verilog test fixture时显示如下，怀疑是模板没有套用上，直接显示的是模板文件，请问怎么办啊，谢谢。 `timescale 1 ns / 1 ps module TEST_gate;
reg <signal1>;
reg [2:0] <signal2>;
wire [3:0] <signal3>;
wire <signal4>; <module_name> <instance_name> (
<port1>,
<port2>
); integer <name1>;
integer <name2>; // The following code initializes the Global Set Reset (GSR) and Global Three-State (GTS) nets
// Refer to the Synthesis and Simulation Design Guide for more information on this process
reg GSR;
assign glbl.GSR = GSR;
reg GTS;
assign glbl.GTS = GTS; initial begin
GSR = 1;
GTS = 0; // GTS is not activated by default
#100; // GSR is set for 100 ns
GSR = 0;
end // Initialize Inputs
`ifdef auto_init initial begin
end `endif
endmodule
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