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- UID
- 824598
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/****************************************************
Header file for the Elan
EM78P156E chip
EM78P156N chip
Title: EM78X156 include file
FileName: EM78x156xx.h
Deion: The Definition of EM78x156
Registers and Bits
Blog: http://51dz.21ic.org
Author: Alin
Date: 2010-01-12
Version: V1.0
****************************************************/
#ifndef _EM78X156XX_H
#define _EM78X156XX_H
typedef unsigned int uint8;
typedef signed int sint8;
typedef unsigned short uint16;
typedef signed short sint16;
typedef unsigned long uint32;
typedef signed long sint32;
#define eni() _asm{eni}
#define disi() _asm{disi}
#define wdtc() _asm{wdtc}
#define nop() _asm{nop}
#define TRUE 1
#define FALSE 0
#define ENABLE 1
#define DISABLE 0
#define ON 1
#define OFF 0
//**********************************************
static unsigned int TCC @0x01:rpage 0;
static unsigned int PC @0x02:rpage 0;
static unsigned int STATUS @0x03:rpage 0;
static unsigned int RSR @0x04:rpage 0;
static unsigned int PORT5 @0x05:rpage 0;
static unsigned int PORT6 @0x06:rpage 0;
static unsigned int ISR @0x0F:rpage 0;
//**********************************************
static io unsigned int P5CR @0x05:iopage 0;
static io unsigned int P6CR @0x06:iopage 0;
static io unsigned int IOC5 @0x05:iopage 0;
static io unsigned int IOC6 @0x06:iopage 0;
static io unsigned int PCR @0x0A:iopage 0; //Prescaler Counter Register
//**********************************************
/*
;CONT(Control Register)
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| / |/INT | TS | TE | PAB |PSR2 |PSR1 |PSR0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
; PAB(预分频分配) -> 0: TCC 1: WDT
; TE(TCC计数方式) -> 0: 0 TO 1 1: 1 TO 0
; TS(TCC计数时钟) -> 0: Cycle Clock 1: TCC Pin
; /INT(中断允许标志) -> 0: masked by DISI or hardware interrupt
; -> 1: enabled by ENI/RETI instructions
;TCC/WDT prescaler bits
;+------+------+------+----------+----------+
;| PSR2 | PSR1 | PSR0 | TCC Rate | WDT Rate |
;+------+------+------+----------+----------+
;| 0 | 0 | 0 | 1:2 | 1:1 |
;+------+------+------+----------+----------+
;| 0 | 0 | 1 | 1:4 | 1:2 |
;+------+------+------+----------+----------+
;| 0 | 1 | 0 | 1:8 | 1:4 |
;+------+------+------+----------+----------+
;| 0 | 1 | 1 | 1:16 | 1:8 |
;+------+------+------+----------+----------+
;| 1 | 0 | 0 | 1:32 | 1:16 |
;+------+------+------+----------+----------+
;| 1 | 0 | 1 | 1:64 | 1:32 |
;+------+------+------+----------+----------+
;| 1 | 1 | 0 | 1:128 | 1:64 |
;+------+------+------+----------+----------+
;| 1 | 1 | 1 | 1:256 | 1:128 |
;+------+------+------+----------+----------+
**/
//**********************************************
static io unsigned int PDCR @0x0B:iopage 0;
static io unsigned int IOCB @0x0B:iopage 0;
/*
;(Pull-down Control Register)
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
;|/PD7 |/PD6 |/PD5 |/PD4 | / |/PD2 |/PD1 |/PD0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| P63 | P62 | P61 | P60 | / | P52 | P51 | P50 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
; 0: Enable 1: Disable
*/
//**********************************************
static io unsigned int ODCR @0x0C:iopage 0;
static io unsigned int IOCC @0x0C:iopage 0;
/*
;(Open-drain Control Register)
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| OD7 | OD6 | OD5 | OD4 | OD3 | OD2 | OD1 | OD0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| P67 | P66 | P65 | P64 | P63 | P62 | P61 | P60 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
; 0: Disable 1: Enable
*/
//**********************************************
static io unsigned int PHCR @0x0D:iopage 0;
static io unsigned int IOCD @0x0D:iopage 0;
/*
;(Pull-high Control Register)
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
;|/PH7 |/PH6 |/PH5 |/PH4 |/PH3 |/PH2 |/PH1 |/PH0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| P67 | P66 | P65 | P64 | P63 | P62 | P61 | P60 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
; 0: Enable 1: Disable
*/
//**********************************************
static io unsigned int WDTCR @0x0E:iopage 0;
static io unsigned int IOCE @0x0E:iopage 0;
/*
;(WDT Control Register)
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
;|WDTE | EIS | / | ROC | / | / | / | / |
;+-----+-----+-----+-----+-----+-----+-----+-----+
; WDTE -> 0: Disable WDT 1: Enable WDT
; EIS -> 0: I/O pin. 1: external interrupt pin
; ROC -> 0: Disable 1: Enable
; ROC is used for the R-option
*/
//**********************************************
static io unsigned int IMR @0x0F:iopage 0;
static io unsigned int IOCF @0x0F:iopage 0;
/*
;IOCF (Interrupt Mask Register)
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| / | / | / | / | / |EXIE |ICIE |TCIE |
;+-----+-----+-----+-----+-----+-----+-----+-----+
; 0: Disable Interrupt 1: Enable Interrupt
; TCIE: TCC overflow interrupt enable
; ICIE: Port 6 input status change interrupt enable
; EXIE: External interrupt enable
*/
//**********************************************
/* STATUS bits
;Bit Define
;STATUS(Status Register)
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| GP2 | GP1 | GP0 | T | P | Z | DC | C |
;+-----+-----+-----+-----+-----+-----+-----+-----+
*/
static bit GP2 @0x03@7:rpage 0;
static bit GP1 @0x03@6:rpage 0;
static bit GP0 @0x03@5:rpage 0; /*general purpose read/write bits*/
static bit T @0x03@4:rpage 0; /*time-out bit*/
static bit P @0x03@3:rpage 0; /*power down bit*/
static bit Z @0x03@2:rpage 0; /*Zero flag*/
static bit DC @0x03@1:rpage 0; /*Auxiliary carry bit*/
static bit C @0x03@0:rpage 0; /*carry flag*/
//**********************************************
/*
;ISR(Interrupt Status Register)
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
;+-----+-----+-----+-----+-----+-----+-----+-----+
;| / | / | / | / | / |EXIF |ICIF |TCIF |
;+-----+-----+-----+-----+-----+-----+-----+-----+
; 0: No Interrupt 1: Interrupt Request
; TCIF: TCC overflow interrupt flag
; ICIF: Port 6 input status change interrupt flag
; EXIF: External interrupt flag
*/
static bit EXIF @0x0F@2:rpage 0;
static bit ICIF @0x0F@1:rpage 0;
static bit TCIF @0x0F@0:rpage 0;
//---------------------------------
/* PORT5 bits */
static bit P53 @0x05@3:rpage 0;
static bit P52 @0x05@2:rpage 0;
static bit P51 @0x05@1:rpage 0;
static bit P50 @0x05@0:rpage 0;
//---------------------------------
/* PORT6 bits */
static bit P67 @0x06@7:rpage 0;
static bit P66 @0x06@6:rpage 0;
static bit P65 @0x06@5:rpage 0;
static bit P64 @0x06@4:rpage 0;
static bit P63 @0x06@3:rpage 0;
static bit P62 @0x06@2:rpage 0;
static bit P61 @0x06@1:rpage 0;
static bit P60 @0x06@0:rpage 0;
//---------------------------------
#endif
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