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求助QUATUSii5.0和Verilog高手帮忙
| 求助QUATUSii5.0和Verilog高手帮忙
我用Verilog编写了一个加密程序如下：
'define del 1
'define enc 8'b10001110
'define width 8
'timescale 1ns/10ps
module encrypt(clk,load,key,data_in,data_out);
input clk;
input load;
input ['width-1:0] key;
input ['width-1:0] data_in;
output ['width-1:0] data_out;
wire clk;
wire load;
wire ['width-1:0] key;
wire ['width-1:0] data_in;
wire ['width-1:0] data_out;
reg ['width-1:0] temp;
assign #'del data_out=temp^data_in;
always @(posedge clk)
begin
if(load)
begin
temp<=#'del key;
end;
else begin
temp['width-1:1]<=#'del temp['width-2:0];
temp[0]<=#'del ^(temp & 'enc);
end
end
endmodule
编译后出现这样的错误Error: Verilog HDL syntax error at encrypt.v(1) near text "'d"; expecting "module", or "macromodule", or "primitive", or "(*", or "config", or "include", or "library"
Error: Verilog HDL syntax error at encrypt.v(4) near text '
Error: Verilog HDL syntax error at encrypt.v(8) near text '
Error: Verilog HDL syntax error at encrypt.v(8) near text "'"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator,
Error: Verilog HDL syntax error at encrypt.v(9) near text '
Error: Verilog HDL syntax error at encrypt.v(9) near text "'"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator,
Error: Verilog HDL syntax error at encrypt.v(10) near text '
Error: Verilog HDL syntax error at encrypt.v(10) near text "'"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator,
Error: Verilog HDL syntax error at encrypt.v(13) near text '
Error: Verilog HDL syntax error at encrypt.v(13) near text "'"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator,
Error: Verilog HDL syntax error at encrypt.v(14) near text '
Error: Verilog HDL syntax error at encrypt.v(14) near text "'"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator,
Error: Verilog HDL syntax error at encrypt.v(15) near text '
Error: Verilog HDL syntax error at encrypt.v(15) near text "'"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator,
Error: Verilog HDL syntax error at encrypt.v(16) near text '
Error: Verilog HDL syntax error at encrypt.v(16) near text "'"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator,
Error: Verilog HDL syntax error at encrypt.v(17): illegal character in decimal number
Warning: Verilog HDL net warning at encrypt.v(17): created undeclared net "l"
Error: Verilog HDL syntax error at encrypt.v(17) near text "data_out"; expecting "="
Error: Verilog HDL syntax error at encrypt.v(22) near text "'d"; expecting an identifier, or a number, or "(", or a real number
Inf Found 0 design units, including 0 entities, in source file encrypt.v |
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