请教cic滤波器的FPGA实现问题（待高手指点） cic, FPGA, 滤波器, 高手, 指点

A120

期待中……

A120

郁闷中……

I designed a CIC filter about 7 or 8 years ago with Xilinx FPGA. It converted 48K audio signal up to 40M. At that time, 40M was almost the fastest Xilinx FPGA could go.

There was an application note on Xilinx website talking about how to implement it on their 6000 family devices. I am not sure if you can still find it any more. Those devices were discontinued long time ago. Good luck!

I designed a CIC filter about 7 or 8 years ago with Xilinx FPGA. It converted 48K audio signal up to 40M. At that time, 40M was almost the fastest Xilinx FPGA could go.

There was an application note on Xilinx website talking about how to implement it on their 6000 family devices. I am not sure if you can still find it any more. Those devices were discontinued long time ago. Good luck!

A120

Could you tell me how to do it.

10+[log5/log2]×4，向上取整数

ssufn@sina.com

有谁自己做过CIC滤波器，不是用IP Core的，能否指教：
如何确定CIC滤波器的位宽？
例：一个4阶CIC抽取滤波器，输入位宽为10位，降采样率为5，四个积分中间变量的位宽如何确定？

[此贴子已经被作者于2003-9-30 16:33:23编辑过]

A120

有复用的方法吗？及两路信号共用一个CIC。