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Error: Top-level design entity "mub_clock" is undefined
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Processing ended: Thu Jan 11 10:18:58 2007
Error: Elapsed time: 00:00:35
Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hud_clock is
Port ( clk : in std_logic;
--jin_wei : out std_logic;
shi_wei : out std_logic_vector(1 downto 0);
ge_wei : out std_logic_vector(3 downto 0));
end hud_clock; architecture Behavioral of hud_clock is
signal shi_current:std_logic_vector(1 downto 0):="00";
signal ge_current :std_logic_vector(3 downto 0):="0000";
--signal jin_current:std_logic:='0';
begin
process (clk)
begin
if (clk'event and clk='1') then
--jin_current<='0';
if (ge_current="0010") and (shi_current="10") then
ge_current<="0000";
shi_current<="00";
--jin_current<='1';
elsif ge_current="1001" then
ge_current<="0000";
shi_current<=shi_current+1;
else ge_current<=ge_current+1;
end if;
end if;
--jin_wei<=jin_current;
shi_wei<=shi_current;
ge_wei<=ge_current;
end process;
end Behavioral;
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