在ISE中插入EDK程序 processor, available, system, create, 数码管

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我做的项目是ps2键盘的扫描放在EDK中完成，而显示程序放在ISE中完成，（注意的是两者之间有通信的）这就要求要有中间信号的功能描述：通过xps中的ps2键盘响应的程序，来获取键盘值，并将此键值通过中间信号送回到ISE中进行在数码管上显示，并且通过串口在屏幕上显现数码管的值。xilinx提供的帮助文件Working with Microprocessor and Peripheral IPXilinx® Platform Studio (XPS), available in the Embedded Development Kit (EDK), allows you to create an embedded processor system. XPS saves your embedded processor system in a Xilinx microprocessor project (XMP) file that you can add as a module to your ISE® project.Following are the basic steps for developing an embedded processor system, which are described in detail below:

• Create an ISE project.
• Add embedded processor source (XMP file) to the ISE project, or create the embedded processor system in XPS.
• Instantiate the XMP module in the top-level HDL file.
• Edit the embedded processor system.
• Associate ELF files with embedded processors in the ISE design.
• Optionally, simulate the embedded processor system.
• Implement the ISE design.
• View implementation results data.
• Generate a BIT file with the hardware and embedded software data.
• Export the hardware design to SDK.

Note EDK is included in the ISE Design Suite: Embedded Edition and System Edition. If you are using a different Edition, you can order EDK separately. For documentation and information on ordering EDK, see the Platform Studio and the EDK Web page. To access the XPS Help, selectHelp > Help Topics in the XPS software.To Create an ISE ProjectTo create an ISE project, see Creating a Project.Note You must select HDL or Schematic as your Top-Level Source Type.To Add an Embedded Processor System to an ISE ProjectWhen you create the embedded processor system for your design in the ISE software, XPS creates an embedded processor project file with a .xmp extension. If you generated your source file using the New Source Wizard and selected Add to Project, you do not need to add the XMP file to your project; it is automatically added to your project and appears in the Hierarchy pane of the Design panel.Note  If you did not automatically add the XMP file to your ISE project, you can add the XMP file to your ISE project, as described in Adding a Source File to a Project. XMP source files mustremain in their original directories. Therefore, you must use the Add Source command rather than Add Copy of Source command when adding XMP files.To Create an Embedded Processor SystemYou can create an embedded processor module in the Project Navigator New Source Wizard as follows:

• Create your embedded submodule as described inCreating a Source File, selecting Embedded Processor as your source type. After you click Finish, Project Navigator opens XPS.Note Embedded Development Kit (EDK) must be installed on your system to enableEmbedded Processor as a source type option. For instructions on configuring XPS on Linux operating systems, see the ISE Design Suite: Release Notes Guide (UG631)available from the Xilinx® website.
• In XPS, create the embedded processor system for your design, as described in Procedures for Embedded Processor Design > Using ISE Project Navigator to Implement Your FPGA Design > Creating an XPS Design as an ISE Submodule in the XPS Help.

Note To include the embedded processor module in the ISE project, the device settings for the embedded processor module must match the device settings of the ISE project. When you use the New Source Wizard to create your embedded processor module, the module automatically inherits the device settings of the ISE project. If you create the module outside of Project Navigator, directly in XPS, you must manually ensure that the device settings match. If Project Navigator detects a device mismatch when the embedded processor module is added to the ISE project, an error is issued and you are given the option to allow Project Navigator to automatically update the target device in the embedded processor module to match the target device in the ISE project.To Instantiate the Embedded Processor System into the ISE DesignIt is recommended that you instantiate XMP source files as lower-level modules in an ISE design as follows:

• In the Hierarchy pane of the Design panel, select the XMP file.
• Do one of the following:

• Run theView HDL Instantiation Templateprocess. Add the code from the template to your top-level design source file, as described inAdding Code Using Language Templates.
• Run theGenerate Top HDL Sourceto create a new HDL file that acts as the top-level source file for your XPS project.

Note An XMP source cannot be the top-level source file in an ISE project. Until the XMP source is properly instantiated in another design module, implementation processes are not available in the ISE software. When the XMP source is properly instantiated in another design module, it appears underneath that module in the Hierarchy pane of the Design panel.To Edit the Embedded Processor SystemAfter you add the XMP file to the ISE project, you can double-click the XMP file in the Hierarchy pane of the Design panel to edit it directly in XPS. If the top-level ports are modified in the XPS project, you must make the necessary changes to the embedded instantiation code.Note Alternatively, you can edit the XMP file as described in Managing the Processor Design (XPS)To Associate ELF Files with Embedded Processors in the ISE DesignIn Project Navigator, ELF files that are associated with the processors in XPS automatically appear under the XMP file in the Hierarchy pane of the Design panel. You can add the ELF files to the project and associate them with individual processors in the XMP source file as follows:

• Select Project > Add Source.
• In the Add Source dialog box, select the ELF file, and click Open.
• In the Adding Source dialog box, specify the Design View Association, whether Implementation, Simulation, or All, and click OK. For more information, see Using the Design Views.
• In theELF/XMP File Associations dialog box, select the processor instance to associate with the ELF file, and click OK.
• （要说明的一点是：elf文件在你的xps文件中的empty_application_0\debuge中）。

Note After the ELF files are added to the project, you can view or modify file associations from the Hierarchy pane. Right-click an ELF file, and select Elf/Xmp File Associations to open the ELF/XMP File Associations dialog box. Alternatively, right-click an XMP file, and select Xmp/Elf File Associations to open the XMP/ELF File Associations dialog box.To Simulate the Embedded Processor SystemIf the XMP source files are instantiated as lower-level modules in your ISE design, you can simulate the design normally, as described in the Simulation Overview, and the Project Navigator and EDK software automatically generate the simulation files necessary for simulating your embedded processor system.You can use the Generate HDL Test Bench (XPS) process to create a template test bench for the XMP embedded processor module. You can then do either of the following:

• Use this test bench directly to simulate the embedded processor module.
• Copy the test bench contents into a higher level design test bench, and modify the paths to simulate the embedded processor module as part of the larger design.

Note The XMP module cannot be simulated directly. It must be instantiated directly in a test bench or instantiated as part of a larger design.To Implement the Embedded Processor SystemAfter you instantiate the XMP source files as lower-level modules in your ISE design, you can implement your design as described in Implementation Overview for FPGAs. After implementation, the embedded processor system is included in the placed and routed design.Following are additional details regarding implementation behavior:

• Synthesis and implementation options are not shared between XPS and Project Navigator.Note When setting Map Properties in Project Navigator, Xilinx recommends that you set the Map Effort Level to High when working with an embedded processor system.
• Process status becomes out-of date in the Processes pane of the Design panel if you modify your embedded processor system in XPS. For example, changes to the MHS file cause the Synthesis and Implement Design processes to become out-of-date. Changes to the User Constraints File (UCF) cause the Implement Design process to become out-of-date. For more information on process status, seeRunning and Stopping Processes.
• Constraints generated in XPS (for the system module as well as instantiated embedded IP) are automatically copied into the ISE project directory as NCF files and are picked up automatically when you implement your design. If you need to modify the constraints associated with the embedded processor system, you must modify the constraints in XPS.

Note For more information, see Copying Constraints to Your ISE Project in the XPS Help.To View Implementation Results DataThe Project Navigator Design Summary provides access to ISE synthesis and implementation reports and messages as well as XPS reports and messages from the PlatGen, LibGen, SimGen and BitInit programs. For more information, see the Design Summary Overview.To Generate a Bitstream File with Processor DataTo generate a bitstream file with processor data, run the Generate Programming File process. This process generates the bitstream for the hardware components of the FPGA device, including the software application data from the ELF files that are part of the project.To Export the Hardware Design to SDKFor embedded software development, the XPS hardware description must be exported to the Software Development Kit (SDK). You can export just the hardware description file without the bitstream and BMM files, or you can export the hardware description file with the bitstream and BMM files. For more information, see Exporting a Hardware Design to SDK.See AlsoIntellectual Property and Cores Overview二、要进行生成xps的顶层文件：三、声明和例化xps文件到顶层COMPONENT system PORT(  fpga_0_RS232_PORT_RX_pin : IN std_logic;  fpga_0_clk_1_sys_clk_pin : IN std_logic;  fpga_0_rst_1_sys_rst_pin : IN std_logic;  ps_ip_0_PS2CLK_pin : IN std_logic;  ps_ip_0_PS2DATA_pin : IN std_logic;           fpga_0_RS232_PORT_TX_pin : OUT std_logic;  ps_ip_0_DATA_pin : OUT std_logic_vector(0 to 15)  ); END COMPONENT;attribute box_type : string;attribute box_type of system : component is "user_black_box";例化：Inst_system: system PORT MAP(  fpga_0_RS232_PORT_RX_pin => fpga_0_RS232_PORT_RX_pin,  fpga_0_RS232_PORT_TX_pin => fpga_0_RS232_PORT_TX_pin,  fpga_0_clk_1_sys_clk_pin => clk,  fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin,  ps_ip_0_PS2CLK_pin => ps_ip_0_PS2CLK_pin,  ps_ip_0_PS2DATA_pin => ps_ip_0_PS2DATA_pin,  ps_ip_0_DATA_pin => x );在端口声明中要添加fpga_0_rst_1_sys_rst_pin : IN std_logic;--注意：在edk中fpga_0_rst_1_sys_rst_pin为高电平时复位，在ise中低电平复位     ps_ip_0_PS2CLK_pin : in std_logic;     ps_ip_0_PS2DATA_pin : in std_logic;       fpga_0_RS232_PORT_RX_pin :in std_logic;     fpga_0_RS232_PORT_TX_pin : out std_logic; 四、ucf文件的问题edk中已经添加了 在你add source时已经添加到user constraints管理器中了，所以不用在添加，因为是在ise中，要更改电平为3.3v和xps一致，否则出错！五、对于在ise和edk之间通信的信号应该如何定义的问题在本实验中使用的是data数据也就是ise中的 ps_ip_0_PS2DATA_pin，你只需要在xps中port目录下将其连接为make external，ucf文件配置就不用了。别忘了在mpd、use_logic、ps_ip文件中配置data为输出端口奥！六、user_logic中的注意事项（一）data <=slv_reg0(16 to 31)；--在plb总线协议中数据是从高位开始读取的c语言中是这样写的# include# include# includemain(){ u32 i;// char i; unsigned long j; while(1) {  //PS_IP_SelfTest(XPAR_PS_IP_0_BASEADDR);  i=PS_IP_mReadSlaveReg0(XPAR_PS_IP_0_BASEADDR, 0);//键盘值读取  PS_IP_mWriteSlaveReg0(XPAR_PS_IP_0_BASEADDR, 0,i);//返回数据到slv——reg0再到ise，在数码管上显示  xil_printf("zhi : %x \r\n",i);                                //通过串口打印     // for(j=0;j<=9999999;j++); }}（二） -- implement slave model software accessible register(s) read mux  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1 ) is  begin    case slv_reg_read_sel is      when "10" => slv_ip2bus_data <=shift1(8 downto 1) & shift2(8 downto 1);--slv_reg0;      when "01" => slv_ip2bus_data <= slv_reg1;      when others => slv_ip2bus_data <= (others => '0');    end case;  end process SLAVE_REG_READ_PROC;我把他换成了直接赋值，原因是当输入和输出共用时，slv_reg0出现了报错，具有多个驱动本人一点小小的总结，如果需要源文件的可以加我：qq:1028875690多交流！转载自：chengmeng2150的博客