下面是卷积码编码VHDL程序,编译时有点问题,麻烦大家帮看一下,不胜感激。 LIBRARY IEEE; USE IEEE.STD_ LOGIC_1164.ALL; ENTITY bianma IS PORT ( datain: IN STD_LOGIC; clk, clr: IN STD_LOGIC; dataout: OUT STD_LOGIC); END bianma; ARCHITECTURE behave OF bianma IS COMPONENT cff2; PORT ( d, clk, clr: IN STD_LOGIC; q: BUFFER STD_LOGIC); END COMPONENT; COMPONEN T xort4; PORT (a, b, c, d: IN STD_LOGIC; q: OUT STD_LOGIC); END COMPONENT; COMPONENT shift6; PORT ( a: IN STD_LOGIC; clk, clr: IN STD_LOGIC; b1, b2, b3, b4: OUT STD_LOGIC); END COMPONENT; COMPONENT switch21; PORT (a, b: IN STD_LOGIC; s: IN STD_LOGIC; y: OUT STD_LOGIC); END COMPONENT; SIGNAL d1, d2, d3, d4, t: STD_LOGIC; BEGIN cffx1: shift6 PORT MAP (a, clk, clr, d1, d2, d3, d4); cffx2: xort4 PORT MAP (d1, d2, d3, d4, t); cffx3: switch21 PORT MAP (a, t, clk, q); END behave; 总是提示:Error (10500): VHDL syntax error at bianma.vhd(16) near text □
[此贴子已经被作者于2007-4-25 8:40:17编辑过] |