新手求教:verilog问题 verilog, 新手, 求教

syy

把北航那本书中的"10010序列检测"改少了F和G状态:

module seqdet(x,z,clk,rst);
input x,clk,rst;
output z;

reg[2:0]state;
wire z;

parameter IDLE=3'd0,
             A=3'd1,
             B=3'd2,
             C=3'd3,
             D=3'd4,
             E=3'd5,
           
assign z=(state==D&&x==0)?1:0;

always@(posedge clk or negedge rst)
if(!rst)
  begin
    state<=IDLE;
  end
else
  casex(state)
    IDLE:if(x==1)
         state<=A;
        
    A:   if(x==0)
         state<=B;
         
    B:   if(x==0)
         state<=C;
         else   state<=A;
    C:   if(x==1)
         state<=D;
         else   state<=IDLE;
    D:   if(x==0)
         state<=E;
         else   state<=A;
    E:   if(x==0)
         state<=C;
         else   state<=A;
            
  default:state<=IDLE;
   endcase
endmodule

结果是红色那句"assign语法出错",怎么回事?

谢谢!