程序是我自己的翻译的以下一段c语言的程序，问题出现在（红字的部分）： 1用寄存器给输出端口赋值的时候，就是我第二个写状态，检测总是出问题， 2在仿真之后波形和预期波形也有点不符， 3新地址的输出想任意指定该如何写 请大家帮我改改，多谢了！～
//------------------------------------------------------
/*if (block_active_in)
{
P_A = imgY[pix_b.pos_y][pix_b.pos_x+0];
P_B = imgY[pix_b.pos_y][pix_b.pos_x+1];
P_C = imgY[pix_b.pos_y][pix_b.pos_x+2];
P_D = imgY[pix_b.pos_y][pix_b.pos_x+3];
P_E = imgY[pix_b.pos_y][pix_b.pos_x+4];
P_F = imgY[pix_b.pos_y][pix_b.pos_x+5];
P_G = imgY[pix_b.pos_y][pix_b.pos_x+6];
P_H = imgY[pix_b.pos_y][pix_b.pos_x+7];
}
else
{
P_A = P_B = P_C = P_D = P_E = P_F = P_G = P_H = img->dc_pred_value;
}
*/
//------------------------------------------------------
`define DATA_NUM 20'd64 //一共8*8矩阵64个数
module transform8(
clock,
reset, //开始读取信号
block_active_in,
img_dc_pred_value, //在读取信号为0时外部输入数据
//io port to external ram
imgY_data_in,
imgY_addr_in,
imgY_noe_in,
p_data_out,
p_addr_out,
p_noe_out,
);
//----------------------------------------------------------------
// Interface Declaration
//----------------------------------------------------------------
input clock;
input reset;
input block_active_in;
input [14:0]img_dc_pred_value;
//io port to external ram //与外部连接端口定义
inout [14:0]imgY_data_in;
input [6:0] imgY_addr_in;
input imgY_noe_in;
output [14:0]p_data_out;
output [6:0] p_addr_out;
output p_noe_out;
//----------------------------------------------------------------
// Interface Declaration
//----------------------------------------------------------------
wire clock;
wire reset; wire block_active_in;
wire [14:0]img_dc_pred_value; //io port to external ram
wire [14:0]imgY_data_in;
wire [6:0] imgY_addr_in;
wire imgY_noe_out; wire [14:0]p_data_out;
wire [6:0] p_addr_out;
wire p_noe_out;
//----------------------------------------------------------------
// Interface Declaration
//----------------------------------------------------------------
reg [3:0] state;
reg [6:0] addr;
reg [14:0] data;
reg [6:1] cnt;
//-----------------------------------------------------------------
// Parameter Declaration
//-----------------------------------------------------------------
parameter IDLE= 3'b000, //定义六个状态；
START_WR_DATA1= 3'b001,
STAT_WR_DATA1_END=3'b010,
START_WR_DATA2= 3'b011,
STAT_WR_DATA2_END=3'b100,
BLOCK_END= 3'b101;
//------------------------------------------
//main block
//------------------------------------------
//state machine
always @ (posedge clock or posedge reset)
begin
if (reset) state<=IDLE;
else
begin
case (state)
IDLE: //有block_active_in信号开始进入写状态
if (block_active_in) state<=START_WR_DATA1;
else state<=IDLE;
//write //写状态，先判断写个数够没够64个，没有继续写
START_WR_DATA1:
begin
if (cnt==`DATA_NUM) state<=STAT_WR_DATA1_END;
else state<= START_WR_DATA1;
end
STAT_WR_DATA1_END: state<= START_WR_DATA2;
//write2
START_WR_DATA2: //写状态2，将写入寄存器的数据输出到输出端口
begin
if (cnt==`DATA_NUM) state<=STAT_WR_DATA2_END;
else state<=START_WR_DATA2;
end
STAT_WR_DATA2_END: state<=BLOCK_END;
BLOCK_END: state<=BLOCK_END;
endcase
end
end
//cnt //计数器
always @(posedge clock or posedge reset)
begin
if (reset) cnt<=0;
else
begin
case(state)
IDLE: cnt<=0;
START_WR_DATA1:
begin
if (cnt == `DATA_NUM) cnt <= 0;
else cnt <= cnt + 1;
end
START_WR_DATA2:
begin
if (cnt == `DATA_NUM) cnt <= 0;
else cnt <= cnt + 1;
end
endcase
end
end //data
always @ (posedge clock or posedge reset)
begin
if (reset) data<=15'b0;
else
begin
case (state)
START_WR_DATA1:
begin
if (block_active_in)
data<=imgY_data_in;
else
data<=img_dc_pred_value;
end
START_WR_DATA2: if (cnt==`DATA_NUM) p_data_out<=data;
endcase
end
end
assign p_data_out=(p_noe_out)?15'b0:data;
assign imgY_data_in=(imgY_noe_in)?data:15'b0; //addr
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
addr<=7'b0;
end
else
begin
if (imgY_noe_in) addr<=imgY_addr_in;
else addr<=0;
end
end
assign p_addr_out=(~p_noe_out)?(addr[6:0]+64):7'b0; //输入新地址
//----------------------------------------------
assign p_noe_out=~imgY_noe_in;
endmodule | 
