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出国和就业- 谁动了你的奶酪?
上海浦东新区后生集成电路培训中心
- 全国第一家以集成电路命名的专业培训中心
- 比利时微电子研究中心培训合作伙伴
- 其高级培训 (Advanced IC Design Training) 在google 中排名第一
集成电路正向设计出国与就业寒假指导班招生简章
出国和就业- 谁动了你的奶酪?
一天等于一年 – 我们帮助你学习学习的能力
培训大纲详见http://www.hwswworld.com 并点击Educational Training页面
一、 简介
燕雀安知鸿鹄之志？无论是直接出国就业，拿奖学金出国，在国内就业或是寻找新的职场跑道，集成电路设计是你的首选敲门砖！
二、特色
- 不仅在技术上引你入门，更给予你选择正确人生道路的启迪
- 以主流厂商 FPGA器件为IC设计的切入点，深入介绍RTL级正向设计及综合技术
- 以业界最流行的硬件描述语言Verilog为正向设计语言，贴近工业实际
- 不是来自学院派的陈旧理论，而是源自工业界的实战演练
- 小班授课，限额20名，对考核合格者颁发上海浦东新区后生集成电路培训中心结业证书
- 设有丰富实验环节（50%为实验时间），并设有专门讨论时端
- 采用中英文授课及讨论，使用英文教程及英文讲义
- 对优秀学员提供可能的推荐就业机会及提供可能的实习机会
三、招生对象：所有有志于集成电路设计者，具有电子工程或计算机专业背景更佳。
四、收费标准：
每人每期3000元，全日制在校生凭有效身份证及学生证享受优惠每人每期1500元。不接受公司报名。其中包括讲课，实验，现场讨论,英文教材及英文讲义。
五、报名联系办法：
电话（周一至周五）：021-5080-2811，5080-2813, 5131-4066, 5131-4177
传真：021-5131-4176 E-mail:toptraining@hwswworld.com
六、上课时间及地点：
1/15,/16，1/17, 1/18, 1/19（上午九点至下午四点），合计30学时。在上海浦东新区郭守敬路498号浦东软件园22217-22219座
Program Agenda (Subject to Change Without Notice)
Agenda
1. Opening Remark2. FPGA Design: The State-of-the-Art2.1 The Y Chart: Behavioral View, Structural View and Physical View2.2 FPGA, ASIC & SoC2.3 From Algorithm to System & m Architecture to Layout2.4 Design Flows: FPGA Flow, ASIC Flow & COT Flow2.5 Migrating FPGA Designs to ASIC/SoC Designs2.6 From PAL, PLD to FPGA2.7 Field Programmable Elements: Logic, Register, Interconnect & I/O2.8 FPGA Architecture Variations: Table-Look-Up Vs. MUX-based2.9 FPGA Architectures at a Glance: Altera, Xilinx & Actel2.10 FPGA Applications in a Nut Shell: Prototyping, Emulation & Production Usage2.11 From Field Programmable (Configurable) to Reconfigurable: Hope or Hyper?3. Verilog for HW Design ¨C Part I3.1 Digital Design Strategies & Techniques3.2 Verilog Syntax Basics3.3 Hierarchical Modeling Concepts in Verilog3.4 Behavioral Subset of Verilog3.5 The Parameterized Design ¨C The 1st Step for Design Reuse3.6 Verilog Coding Styles4. FPGA HW Architecture In Depth4.1 Mainstream FPGA Architectures4.2 Mainstream FPGA Design Tools4.3 Mainstream FPGA Design Flows5. Verilog for HW Design ¨C Part II5.1 Structural Subset of Verilog5.2 Useful Modeling Techniques in Verilog5.3 Timing & Delays in Verilog 5.4 Verilog PLI5.5 Verilog Test Fixtures6. The Essence of RTL Design6.1 Controller & Datapath6.2 Controller: Hardwired Vs. Programmable 6.3 FSM: Mealy Machine Vs. Moore Machine6.4 Datapath Elements at a Nut Shell6.5 Bus Architectures6.6 Memory Organization6.7 Introduction to Using ASM for RTL Design7. RTL Design with ASM7.1 ASM Notations7.2 The Theory behind ASM7.3 Scheduling, Resource Allocation & Binding7.4 Mini- Case Study: Design a Square Root Approximation (SQA) Block in ASM8. Open Discussion
Lab 1 Design, Compile and Verify N Bit ALU Consists of Adder, Subtract or, Logic Unit & Decoder
1. Algorithms in FPGA Logic Synthesis1.1 Design Entry: Text based Vs Graphic based1.2 Timing Constraints Entry & Waveform Entry1.3 Assigning Device Types1.4 Assigning Pin, Location & Chip1.5 Compilation for Logic Synthesis: Technology Independent Optimization & Technology Mapping2. Algorithms in FPGA Design Verification2.1 Functional Simulation2.2 Timing Simulation2.3 Static Timing Analysis3. Verilog Design for HW Design ¨C Part III3.1 Verilog Hierarchy3.2 Built-In Logic Primitives3.3 User-Defined Primitives (UDP)3.4 Library Parameterized Modules (LPM)3.5 Latches and Flipflops3.6 Blocking and Non-blocking Assignments3.7 Miscellaneous Verilog Modeling Tricks4. Physical Synthesis in FPGA Design4.1 Floorplanning4.2 Placement & Routing4.3 Manual Layout Editing & Optimization5. Verilog for HW Design ¨C Part IV5.1 Simulation View Vs Synthesis View5.2 Synthesizable Subset of Verilog5.3 Synthesizable Subset of Verilog 5.4 Verilog Synthesis Styles5.5 RTL Coding Styles for Verilog5.6 Design for Performance/Cost Trade-off5.7 Design for Design Reuse6. Real Life Digital Design Strategies and Techniques6.1 Synchronous Logic Rules6.2 Clock Strategies6.3 Design for Test Issues6.4 Area/Delay Optimization7. Open Discussion
Lab2 Design, Compile and Verify a N Bit Shift-Subtract-based Division Machine based on N Bit ALU & Controlled by a FSM-based Controller
1. Issues in Real Life Digital Design1.1Verilog Hierarchy Revisited1.2 Tri-state Signals and Buses1.3 Reset, Preset, Tri-state and Bi-directional Signals1.4 Priority Encoders1.5 Area/Speed Optimization in Synthesis1.6 Trade-off between Operating Speed and Latency1.7 Delays in FPGA Elements1.8 Design Partitioning1.9 Scalable and Parameterized Design2. Building Blocks in Real Life Digital Design2.1 Decoders and Encoders2.2 Registers and Latches2.3 Adders and Sub tractors2.4 Multipliers and Dividers2.5 Counters and Simple Arithmetic Functions2.6 Finite State Machines Revisited2.7 Register Files2.8 ROM, RAM2.9 FIFO and UART3. Real World Design: Tools, Techniques and Trade-offs3.1 Hybrid Design Entries3.2 Assigning Devices3.3 Assigning Pins3.4 Optimization Options3.5 Mapping Options3.6 RTL Simulation Vs Post-Layout Simulation & Their Options3.7 Logic Level Timing Report/Post-Layout Timing Report3.8 FPGA Design Flow Issues4. Libraries, Reusable Modules and IP4.1 Keys to Increased Productivity4.2 Library Elements4.3 Design Reuse and Design for Reuse4.4 The Reuse Methodology Manual4.5 IP based FPGA Design5. Open Discussion
Lab 3 Design, Compile and Verify a N Bit Division Machine IP with read FIFO IP and Write FIFO IP
Floating Lab1: Design, Compile and Verify a N Bit Division Machine IP with read SDRAM IP and Write SDRAM IP in Non-pipelined Mode
Floating Lab2: Design, Compile and Verify a N Bit Division Machine IP with read SDRAM IP and Write SDRAM IP in Pipeline Mode |
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