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- UID
- 95028
- 性别
- 男
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| 这个是教材上的一个程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity conversion is
port ( input : in std_logic_vector(7 downto 0);
con_flag: out boolean;
output : inout integer);
end conversion;
architecture behave of conversion is
procedure vector_to_int
( a : in std_logic_vector;
x_flag: out boolean;
q : inout integer)is －－这里定义q为inout的原因是？
begin
q:=0;
x_flag:=false;
for i in a'range loop
q:=q*2;
if (a(i)='1') then
q:=q+1;
elsif (a(i)/='0') then
x_flag:=true;
end if;
end loop;
end vector_to_int;
begin
process(input)
variable tmp1 : boolean;
variable tmp2 : integer;
begin
vector_to_int(input,tmp1,tmp2);－－这里如果不用tmp1，tmp2，直接用con_flag
con_flag<=tmp1; －－和output，有什么区别呢？
output<=tmp2;
end process;
end behave;
再有就是请大家介绍一下学习vhdl的经验好吗？应该如何学习才能学的比较好呢？呵呵：）谢谢了 |
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Respect your teacher is in the same way as respecting knowledge and yourself.
------Lunne |
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