An alias is just an alternate name for a slice
of an existing variable or signal. 呵呵 David Bishop said it best:
"VHDL was written by a bunch of software guys who knew nothing about
designing hardware. We beat on it until you could do hardware with it.
Verilog was written by a bunch of hardware guys who knew nothing about
designing software. We beat on it until you could do software with it.
Neither does the job they were originally intended to do, but they work." | 
