CLKSEL = 0; /* Select clock source from XTAL and set bits in CLKSEL reg. */
/* PLLCTL: PLLON=0 */
PLLCTL &= 0x40; /* Disable the PLL */
/* SYNR: ??=0,??=0,SYN5=0,SYN4=0,SYN3=0,SYN2=0,SYN1=0,SYN0=1 */
SYNR = 1; /* Set the multiplier register */
/* REFDV: ??=0,??=0,??=0,??=0,REFDV3=0,REFDV2=0,REFDV1=0,REFDV0=0 */
REFDV = 0; /* Set the divider register */
/* PLLCTL: CME=0,PLLON=1,AUTO=1,ACQ=1,??=0,PRE=0,PCE=0,SCME=0 */
PLLCTL = 0x70;
while(!CRGFLG_LOCK) {}; /* Wait */
/* CLKSEL: PLLSEL=1 */
CLKSEL = 0x80; /* Select clock source from PLL */
//此时PLL的输出频率为44.2368，总线频率为22.1184。
[此贴子已经被strongchen于2006-9-22 12:26:40编辑过] | 
