我做了一个如下的程序，看看符合你的要求吗？
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test is
port(
clk:in std_logic;
reset:in std_logic;
a:in std_logic_vector(1 downto 0);
b:in std_logic_vector(1 downto 0);
c:in std_logic_vector(1 downto 0);
d ut std_logic_vector(4 downto 0)
);
end test;
architecture rtl of test is
signal pc:std_logic_vector(4 downto 0);
signal i:std_logic_vector(1 downto 0);
signal en:std_logic;
begin
process(clk,reset)
variable add_a:std_logic_vector(4 downto 0);
variable add_b:std_logic_vector(4 downto 0);
variable temp:std_logic_vector(4 downto 0);
begin
add_a:="000"&a;
if(reset='0')then
pc<="00000";
i<="00";
en<='1';
elsif (clk'event and clk='1')then
if(en='1')then
if(i<=c)then
add_b(3 downto 0):=i*b;
add_b(4):='0';
else
en<='0';
end if;
temp:=add_a+add_b;
if(pc=temp)then
d<=pc;
i<=i+1;
pc<=pc+1;
else
pc<=pc+1;
end if;
end if;
end if;
end process;
end rtl; |
