新手，请教一个VHDL程序编译报错问题 计数器, 程序

yuchengze

以下程序希望实现的功能是，若CM脉冲以1000个时钟(sysclk)为周期到来一次，CutMark就一直保持低电平，若CM某次未到来，那么，CutMark在此刻将被置高，提示CM丢失。实现原理是：CM每次到来就将计数器CMcounter清零，若某次CM丢失，计数器将计到1020，此时置高CM。

源码如下：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CMprocess is port
(
sysclk:    in   std_logic;
glbrst:    in   std_logic;
CM:        in   std_logic;
CutMark: out std_logic;

Cen:     out std_logic;
CounterVal: out std_logic_vector(12 downto 0)
);
end CMprocess;

architecture behavior of CMprocess is

signal CMcounter: std_logic_vector(12 downto 0);
signal Cen1:         std_logic;
signal CM1:          std_logic;
signal CutMark1:   std_logic;

CONSTANT CMLOST: std_logic_vector(12 downto 0) := "0001111111100"; --1020

Begin

CMprocess: process(sysclk,glbrst)

begin

  if rising_edge(sysclk) then
  
   CM1 <= CM;
   
  end if;

  if glbrst = '0' then
  
   Cen1 <= '0';
   CutMark1 <= '0';
   CMcounter <= (others => '0');
   
  elsif rising_edge(sysclk) then
   
   if CM1 = '0' then --第一个CM到来就使能计数器
   
    Cen1 <= '1';
   
   end if;
  
  end if;
-----------------------------------------------------------  
  if CM1 = '0' then --每次CM到来就清零计数器

   CMcounter <= (others => '0');
   
  elsif rising_edge(sysclk) then

   if Cen1 = '1' then
   
    if CMcounter < CMLOST then --否则在计数器使能和未计到1020情况下继续计数

     CMcounter <= CMcounter + '1';
   
       else

     CutMark1 <= '1';
   
       end if;
   
      end if;
      
  end if;
-----------------------------------------------------------
end process;

Cen <= Cen1;
CutMark <= CutMark1;
CounterVal <= CMcounter;