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- UID
- 113770
- 性别
- 男
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| 我用XC9572想实现一个64位移位寄存器的功能,用verilog编写的程序,综合仿真的时候在FIT这个步骤居然说实现这个需要92个宏单元,想请高手指点一下:寄存器变量是不是每位都需要占用一个宏单元?为什么会出现这种情况呀,怎么解决呀
module shixu(data,clk);
output [64:1] data;
input clk;
reg fr=0;
reg [20:1] j=0;
reg [64:1] data=-1;
reg [7:1] counter=0;
always@(posedge clk)
begin
if(j==1000000)
begin
j<=0;fr<=~fr;
end
else
j<=j+1;
end \\2M的晶振分频到1HZ
always@(posedge fr)
if(counter==1)
begin
data[counter]<=0;
counter=counter+1;
data[64]<=1;
end
else if(counter==64)
begin
data[counter]<=0;
data[counter-1]<=1;
counter=1;
end
else
begin
data[counter]<=0;
data[counter-1]<=1; counter=counter+1;
end\\实现移位寄存器功能
endmodule |
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