library ieee;
use ieee.std_logic_1164.all;
entity latch373 is
port(
d:in std_logic_vector(7 downto 0);
oe,g:in std_logic;
q0,q1,q2,q3,q4,q5,q6,q7 ut std_logic
--qut std_logic_vector(7 downto 0)
);
end latch373;
architecture rtl of latch373 is
signal q_temp: std_logic_vector(7 downto 0);
begin
q0<=q_temp(0);
q1<=q_temp(1);
q2<=q_temp(2);
q3<=q_temp(3);
q4<=q_temp(4);
q5<=q_temp(5);
q6<=q_temp(6);
q7<=q_temp(7);
process(oe,g,d)
begin
if(oe='0')then
if(g='1')then
q_temp<=d;
end if;
else
q_temp<="zzzzzzzz";这个地方有问题，而且大小写不一样的错
end if;
end process;
end rtl;
哪位大侠帮忙看看阿 |
