[原创]FPGA/CPLD系列实验教程:实验一点亮LED
 
- UID
- 115233
- 性别
- 男
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要是能把图片加上最好啦!~
这个实验的VHDL源代码:
--lightled1
library ieee;
use ieee.std_logic_1164.all;
entity ledlight1 is
port(led ut std_logic_vector(7 downto 0));
end;
architecture behav of ledlight1 is
begin
led<="10101010";
end; |
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