不知道在map report 中的等效门数是怎么算出来的！我用V4_lx200 和V2pro_6000实现的两个不同的设计。大小相差很多。但是map report 中报出来的却几乎一样！LX200和V2pro6000相差可是数倍啊！请高人指点
Target Device : xc4vlx200
Target Package : ff1513
Target Speed : -10
Mapper Version : virtex4 -- $Revision: 1.26.6.4 $
Mapped Date : Wed Nov 23 15:49:01 2005
Design Summary
--------------
Number of errors: 0
Number of warnings: 14
Logic Utilization:
Total Number Slice Registers: 28,199 out of 178,176 15%
Number used as Flip Flops: 28,198
Number used as Latches: 1
Number of 4 input LUTs: 87,920 out of 178,176 49%
Logic Distribution:
Number of occupied Slices: 55,530 out of 89,088 62%
Number of Slices containing only related logic: 55,530 out of 55,530 100%
Number of Slices containing unrelated logic: 0 out of 55,530 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 96,284 out of 178,176 54%
Number used as logic: 87,920
Number used as a route-thru: 1,258
Number used as 16x1 ROMs: 732
Number used as Shift registers: 6,374
Number of bonded IOBs: 105 out of 960 10%
Number of BUFG/BUFGCTRLs: 7 out of 32 21%
Number used as BUFGs: 4
Number used as BUFGCTRLs: 3
Number of DSP48s: 15 out of 96 15%
Number of DCM_ADVs: 1 out of 12 8%
Total equivalent gate count for design: 1,277,705
Additional JTAG gate count for IOBs: 5,040
Peak Memory Usage: 3111 MB
Target Device : x2v6000
Target Package : ff1517
Target Speed : -4
Mapper Version : virtex2 -- $Revision: 1.16 $
Mapped Date : Fri Feb 25 11:02:39 2005
Design Summary
--------------
Number of errors: 0
Number of warnings: 5
Logic Utilization:
Number of Slice Flip Flops: 18,473 out of 67,584 27%
Number of 4 input LUTs: 37,297 out of 67,584 55%
Logic Distribution:
Number of occupied Slices: 24,268 out of 33,792 71%
Number of Slices containing only related logic: 24,268 out of 24,268 100%
Number of Slices containing unrelated logic: 0 out of 24,268 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 39,690 out of 67,584 58%
Number used as logic: 37,297
Number used as a route-thru: 2,393
Number of bonded IOBs: 285 out of 1,104 25%
IOB Flip Flops: 179
Number of Block RAMs: 9 out of 144 6%
Number of MULT18X18s: 31 out of 144 21%
Number of GCLKs: 15 out of 16 93%
Total equivalent gate count for design: 1,150,800
Additional JTAG gate count for IOBs: 13,680
Peak Memory Usage: 522 MB |
