一切从零开始

逻辑结构错误
首先if(clk'event and clk<='1')then中clk='1'就可以了，不是信号赋值
其次下面的结构不对，
if(clk'event and clk<='1')then
if(xishu120000<="11101010011000000")then
xishu120000<="00000000000000000";
s100s<=not s100s;
else
xishu120000<=xishu120000+"1";
end if;
s100<=s100s;
end process;
我比较喜欢用case 语句，也可以这样
process(clk)
variable count:integer range 0 to 120000;
variable s100s:std_logic;
begin
if(clk'event and clk='1')then
 case count is
   when 120000=>count:=0;
      s100<=s100s;
      s100s:=not s100s;
  when others=>count:=count+1;
 end case;
end if;
end process;