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新手又来求助

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors.  Please refer to the
-- applicable agreement for further details.


-- Generated by Quartus II Version 5.1 (Build Build 176 10/26/2005)
-- Created on Sat Jan 06 00:37:33 2007

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

--  Entity Declaration

ENTITY ag IS
 -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
 ORT
 (
  clk : IN STD_LOGIC;
  dout : OUT STD_LOGIC_VECTOR(18 downto 0)
 );
 -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 
END ag;


--  Architecture Body

ARCHITECTURE ag_architecture OF ag IS

 
BEGIN
process(clk)
variable count:integer range 0 to 19;
variable c:std_logic_vector(18 downto 0);
begin
 if(clk'event and clk='0')then
  case count is
   when 19=>count:=0;
     c:="0000000000000000001";
   when others=>c:=(others=>'0');
       c(count):='1';
      count:=count+1;
  end case;
  dout<=c;
 end if;
end process;
     
END ag_architecture;

这个你可以试一下,另外你可以试一下把tmp<=tmp+tmp;改成c:=c+c;tmp<=c;--c是变量,

每一天都是新的开始,每一天都有新的收获
你可以看一下信号量辅值的定义,我也说不好
每一天都是新的开始,每一天都有新的收获
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