a few approches to avoid this or similar:
1) Unused pins should not float. Floating input receivers can reside at a totally arbitrary level and may induce input stages to draw as much as 10 mA per pin. This factor is easily remedied by driving the pins to known
CMOS levels. One easy way to do this is to simply invoke the User Programmable Ground Option (UPG). Care must be taken that these pins are indeed unused
and not reserved for future functionality. They will be driven to ground and if wished, may be externally attached to the PCB ground to provide additional chip
grounding.
2) Use global resources where possible. Overusing clocks, sets, resets and OEs can add up in the power budget.
3) Restricting the voltage swing of the output stage will lower the power consumed. It may impact other chips that expect a larger voltage range, but can dramatically lower power consumed in the CPLD.
4) Because most CPLD users seek raw speed, the defaults with macrocells
configured for high speed. Which also takes the most current. By carefully selecting only those macrocells that need be in high speed mode.
5) Minimize Function Blocks used. If a single macrocell occupies a Function Block, the Function Block will be turned “on”. When this occurs, all unused macrocells in that FB will be powered up to at least the low power Bitline high condition. |
