如何仿真IP核（建立modelsim仿真库完整解析）:资料
|
 
- UID
- 131591
- 性别
- 男
|
|
|
|
|
|
|
- UID
- 131591
- 性别
- 男
|
我是在ISE中直接调用Modelsim进行仿真的，IP核已经例化。但在仿真中还是报错
给解释一下吧
Loading work.testfifo_v
# Loading work.top1
# ** Error: (vsim-3033) top1.v(54): Instantiation of 'myfifo' failed. The design unit was not found.
# Region: /testfifo_v/uut
# Searched libraries:
# d:\Modeltech_xe\win32xoem/../xilinx/verilog/xilinxcorelib_ver
# d:\Modeltech_xe\win32xoem/../xilinx/verilog/unisims_ver
# work
# Loading work.glbl
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./testfifo_v.fdo PAUSED at line 8 |
|
|
|
|
|
