arrally

大家帮我看看是那里出错了,我是第一次使用这软件的,照论坛上的7.1中文教程建了新的PROJECT(MYDAC),然后在XC9572--击右键,选ADD SOURCE,出现图片1,选DAC24VHD.VHD,如图,接着就出现了图3的画面,如果选TESTVHD.VHD.则出现图4,也是提示有问题
DAC24VHD的文件
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC_24 is
Port ( bck : in std_logic;
lrck : in std_logic;
data : in std_logic;
ch : in std_logic;
test : in std_logic;
dout : out std_logic_vector(23 downto 0));
end DAC_24;

architecture Behavioral of DAC_24 is

signal latch : std_logic_vector(23 downto 0);
signal n : integer range 0 to 63;
signal lrck_1,lrck_2 : std_logic;
signal test_bit:std_logic :='0';
begin
process (bck,lrck,data,ch,test)
begin
if (bck'event and bck='1') then
lrck_1 <= lrck;
lrck_2 <= lrck_1;
if (test='0') then
latch<=(0=>test_bit,others=>test_bit);
elsif ((ch='1' and n>=8 and n<=31) or (ch='0' and n>=32+8 and n<=32+31)) then
latch <= latch(22 downto 0) & data;
end if;
end if;
if (bck'event and bck='0') then
if (lrck_2 ='1' and lrck_1='0') then
n<=1 ;
elsif (n=63) then
n<=0;
else
n<=n+1;
end if;
end if;

if (lrck'event and lrck='1') then
dout <= (not latch(23)) & latch(22 downto 0);
test_bit <= not test_bit;
end if;
end process;

end Behavioral;
[upload=image/pjpeg]uploadImages/ise1.jpg[/upload][upload=image/pjpeg]uploadImages/ise2.jpg[/upload][upload=image/pjpeg]uploadImages/ise3.jpg[/upload][upload=image/pjpeg]uploadImages/ise4.jpg[/upload]