waterlily

if(reset)
my_counter<=0;
flag<=0;
else if(add and !flag)
my_counter<=my_counter+1;
flag<='1';
else if(minus and !flag)
my_counter<=my_counte-1;
flag<='1';
else if (!minus or !add)
flag<='0';
else
my_counter<=my_counter;
大概这个意思吧！因为一直用vhdl,这样写verilog如果语法不对再改改