library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SYFIFO is
generic(FIFO_Depth : integer :=10; FIFO_Width : integer :=10);
port(
read_clock_in : in std_logic;
write_clock_in : in std_logic;
read_enable_in : in std_logic;
write_enable_in : in std_logic;
full_out : out std_logic;
empty_out: out std_logic;
reset_in : in std_logic;
write_data_in : in std_logic_vector(FIFO_Width-1 downto 0);
read_data_out : out std_logic_vector(FIFO_Width-1 downto 0));
end SYFIFO;
architecture FIFOArc of SYFIFO is
type BlockRam is array (0 to FIFO_Depth-1) of std_logic_vector(FIFO_Width-1 downto 0);
signal RAM : BlockRam;
signal read_clk : std_logic;
signal write_clk : std_logic;
signal read_enable : std_logic;
signal write_enable : std_logic;
signal full : std_logic;
signal empty : std_logic;
signal reset : std_logic;
signal read_addr : integer range 0 to FIFO_Depth-1;--std_logic_vector(9 downto 0);
signal write_addr : integer range 0 to FIFO_Depth-1;--std_logic_vector(9 downto 0);
begin
read_enable <= read_enable_in;
write_enable <= write_enable_in;
read_clk <= read_clock_in;
write_clk <= write_clock_in;
full_out <= full;
empty_out <= empty;
reset <= reset_in;
-------------------------------------------------------
--读地址指针信号的产生
-------------------------------------------------------
proc1:process(read_clk,reset)
begin
if (reset='1') then
read_addr <= FIFO_Depth-1;
elsif (read_clk'event and read_clk='1') then
if (read_enable='1' and empty='0') then
if (read_addr=FIFO_Depth-1) then
read_addr<=0;
else
read_addr <= read_addr+1;
end if;
end if;
end if;
end process proc1;
-------------------------------------------------------
--写地址指针信号的产生
-------------------------------------------------------
proc2:process(write_clk,reset)
begin
if (reset='1') then
write_addr <= 0;
elsif (write_clk'event and write_clk='1') then
if (write_enable='1' and full='0') then
if(write_addr=FIFO_Depth-1) then
write_addr <=0;
else
write_addr <= write_addr+1;
end if;
end if;
end if;
end process proc2;
--------------------------------------------------------
---读操作
--------------------------------------------------------
proc3:process(read_clk)
begin
if (read_clk'event and read_clk='1') then
if (read_enable='1' and empty='0') then
read_data_out <= RAM(read_addr);
end if;
end if;
end process proc3;
-------------------------------------------------------
----写操作
--------------------------------------------------------
proc4:process(write_clk)
begin
if (write_clk'event and write_clk='1') then
if (write_enable='1' and full='0') then
RAM(write_addr) <= write_data_in;
end if;
end if;
end process proc4;
------------------------------------------------------
--空标志和读使能信号的产生
------------------------------------------------------
proc5:process(read_clk,reset)
begin
if (reset='1') then
empty <= '1';
read_enable <= '0';
elsif (read_clk'event and read_clk='1') then
if ((read_addr=write_addr-2 or (read_addr=FIFO_Depth-1 and write_addr=1) or (read_addr=FIFO_Depth-2 and write_addr=0)) and (read_enable='0' and write_enable='1')) then
empty <='1';
read_enable <= '0';
elsif (empty='1' and write_enable='0') then
empty <='0';
read_enable <= '1';
end if;
end if;
end process proc5;
------------------------------------------------------
--满标志和写使能信号的产生
------------------------------------------------------
proc6:process(write_clk,reset)
begin
if (reset='1') then
full <= '0';
write_enable <= '0';
elsif (write_clk'event and write_clk='1') then
if (read_addr=write_addr and read_enable='1' and write_enable='0') then
full <='1';
write_enable <= '0';
elsif (full='1' and read_enable='0') then
full <='0';
write_enable <= '1';
end if;
end if;
end process proc6;
---------------------------------------------------------
---输出空满标志信号
---------------------------------------------------------
proc7:process(write_clk)
begin
if (write_clk'event and write_clk='1') then
full_out <= full;
empty_out <= empty;
end if;
end process proc7;
end FIFOArc;
，这个程序不能综合，急急急！！！！ | 
