陈石亮

`timescale 1ns/1ns

module compare_test();
reg [3:0] ta,tb;
wire tf;

compare_one cm(tf,ta,tb);

parameter step=100;

initial
begin
ta=0;tb=0;
#step ta=4'd5;
#step tb=4'd6;
#step ta=4'd6;
#step ta=4'd7;
#step tb=4'd8;
#step $stop;
end
endmodule