//------------------------------------------------------
//+generate 1ms
//clk=40Mhz
`define MS_VALUE 40000
reg[15:0] ms_counter;
reg ms;
always @ ( posedge clk or posedge reset )
begin
if( reset )
begin
ms<=0;
ms_counter <= `MS_VALUE;
end
else
begin
ms_counter<=ms_counter-1;
if(ms_counter==0)
begin
ms_counter <= `MS_VALUE;
ms <= ~ms;
end
end
end
//-generate 1ms
//------------------------------------------------------ |
