为什么这样定义的计数器不能正确功能仿真,好郁闷好几天了,是不是对inout类型不能综

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- 149611
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为什么这样定义的计数器不能正确功能仿真,好郁闷好几天了,是不是对inout类型不能综
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is port( clk: in std_logic; count: inout std_logic_vector(15 downto 0) ); end counter; architecture Behavioral of counter is begin process(clk) begin if (clk='1') and (clk'event) then count<=count+1; end if; end process; end Behavioral; |
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