[求助]请大家再次帮忙看看以下VHDL编译时的警告信息 VHDL, 编译, 警告, 求助, 帮忙

zhtt0865

用DSP-Builder建立模型，转换VHDL后经编译出现以下警告信息：
1.Warning (10036): Verilog HDL or VHDL warning at DSPBUILDER.VHD(4364): object "svcc" assigned a value but never read
2.Warning: Resynthesizing Cyclone or Stratix WYSIWYG primitives into Cyclone II WYSIWYG primitives; however, resynthesized WYSIWYG primitives may not produce optimal compilation results.
3.Warning: Found 14 output pins without output pin load capacitance assignment
4.Warning: Found pins functioning as undefined clocks and/or memory enables
在modelsim仿真，输出波形为零。不知道VHDL哪部分出问题了，请各位高手帮忙，在此先谢谢了