变量声明有效性问题

变量, 有效性, 声明

我对一个过程做如下定义的时候，出来个错误提示 Error (10482): VHDL error at fft_mult.vhd(38): object "a_ext" is used but not declared，显然是因为使用了a_ext ，而a_ext 却在PROCEDURE后定义引起的

PROCEDURE signed_add (signal A,B:IN std_logic_vector;
  signal C:OUT std_logic_vector) is
BEGIN
  a_ext <= a(WIDTH-1) & a;
    b_ext <= b(WIDTH-1) & b;
    sum <= a_ext + b_ext;

    c <= sum(WIDTH downto 1);
END PROCEDURE signed_add;
signal a_ext        :std_logic_vector(A'high+1 downto 0);
    signal b_ext        :std_logic_vector(A'high+1 downto 0);
    signal sum          :std_logic_vector(A'high+1 downto 0);

为了克服这个问题，我把变量的声明放到PROCEDURE的前面，如下：

signal a_ext        :std_logic_vector(A'high+1 downto 0);
    signal b_ext        :std_logic_vector(A'high+1 downto 0);
    signal sum          :std_logic_vector(A'high+1 downto 0);
ROCEDURE signed_add (signal A,B:IN std_logic_vector;
  signal C:OUT std_logic_vector) is
BEGIN
  a_ext <= a(WIDTH-1) & a;
    b_ext <= b(WIDTH-1) & b;
    sum <= a_ext + b_ext;