请教双端口RAM IP核使用的问题 RAM, 端口, 请教

godjohsn

利用xilinx的Dual Port Block Memory 双端口IP核做一个读写RAM,设置为Port A写入,Port B读出:
Memory Size:
Width A:16 Depth:12
Width B:16 Depth:12

Port A Options:
Configuration: Write Only
Write Mode:Read After Write

Port B Options:
Configuration: Read Only

模块程序:
module interleaver(clk, reset, x, y);
input clk; //clk和x同频同相
input reset;
input [15:0] x;
output [15:0] y;

reg [3:0] addra, addrb; //RAM的控制地址
wire [3:0] addrat, addrbt;

always @(posedge clk) begin
if(!reset) begin
addra <= 0;
addrb <= 0;

end
else begin
if(addra == 11) //顺序依次将x写入BLOCK RAM
addra <= 0;
else
addra <= addra + 1;
if(addrb == 11)
addrb <= 0;
else
addrb <= addrb + 1;
end
end



block_ram block_ram(
.addra(addra),
.addrb(addrb),
.clka(clk),
.clkb(clk),
.dina(x),
.doutb(y),
.wea(reset));

endmodule

测试程序:
module test_ram_v;

// Inputs
reg clk;
reg reset;
reg [15:0] x;

// Outputs
wire [15:0] y;

// Instantiate the Unit Under Test (UUT)
interleaver uut (
.clk(clk),
.reset(reset),
.x(x),
.y(y)
);



initial begin
// Initialize Inputs
clk = 0;
reset = 0;
x = 0;

// Wait 100 ns for global reset to finish
#100;
reset = 1;
#100;
x = 16'b1001000000000000;
#100;
x = 16'b1001000000000001;
#100;
x = 16'b1001000000000010;
#100;
x = 16'b1001000000000011;
#100;
x = 16'b1001000000000100;
#100;
x = 16'b1001000000000101;
#100;
x = 16'b1001000000000110;
#100;
x = 16'b1001000000000111;
#100;
x = 16'b1001000000001000;
#100;
x = 16'b1001000000001001;
#100;
x = 16'b1001000000001010;
#100;
x = 16'b1001000000001011;
end

always #50 clk = ~clk;

endmodule

可是输出y全为未知状态,谁能帮看看什么问题?