| library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ch_2 is
port(
cs : in std_logic;
in3 : in std_logic_vector(2 downto 0);
out8 : out std_logic_vector(7 downto 0)
);
end ch_2;
architecture a of ch_2 is
begin
p1:process (cs,in3)
begin
if (cs = '0')
then
case in3 is
when "000" => out8<="00000001";
when "001" => out8<="00000010";
when "010" => out8<="00000100";
when "011" => out8<="00001000";
when "100" => out8<="00010000";
when "101" => out8<="00100000";
when "110" => out8<="01000000";
when "111" => out8<="10000000";
when others => out8<="0000000";
end case;
else
out8 <= "11111111";
end if;
end process p1;
end a; |
