void clear_CPU_operation_detection (void)
{
LVRC = 0x35; /* clears CPU operation detection */
}
/*---------------------------------------------------------------------------
CAN0
/*---------------------------------------------------------------------------*/
void Init_can(void)
{
CSR0 = 0x81; /* bit 7: enable transmit output pin */
/* bit 0: stop bus operation */
while (!CSR0_HALT)
clear_CPU_operation_detection ();
TCANR0 = 0xffff; /* cancel all Transmissions */
BVALR0 = 0; /* all message buffer are invalid */
BTR0 = 0x3A43; /* <<< set bit timing BTR_16M_250k_16_68_2*/
CSR0 = 0x0080; /* activate can bus operation */
while (CSR0_HALT) /* wait for Bus-connection */
clear_CPU_operation_detection ();
AMR00 = 0; /* <<< acceptance mask definition 0 */
AMR10 = 0; /* <<< acceptance mask definition 1 */
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
BVALR0 = 0X0000; /* message buffer are invalid */
IDER0 = 0X000F; /* <<< 0:11bit标准帧 1:29bit indentifier扩展帧 */
IDRX0(0) = Tacho_ID; /* <<< ID e.g. 0x2000 = ID #1 */
/* (11bit-IDs uses Bit 28..18 */
/* (29bit-IDs uses Bit 28...0 */
/* see Utility Bitmixer
/* or use defines: e.g. IDR(1) = MSG2STD(1); */
IDRX0(1) = Oil_ID;
IDRX0(2) = Coolant_ID;
IDRX0(3) = Power_ID;
AMSR0_AMS0 = 0; /* <<< Acceptance Mask: */
/* 0 : full bit compare (full can) */
/* 1 : full bit mask (basic can) */
/* 2 : use acceptance mask 0 */
/* 2 : use acceptance mask 1 */
AMSR0_AMS1 = 0;
AMSR0_AMS2 = 0;
AMSR0_AMS3 = 0;
TIER0 = 0X0000; /* <<< 0: diasble / 1: enable Trx-Interrupt */
RIER0 = 0X000F; /* <<< 0: diasble / 1: enable RCE-Interrupt */
RFWTR0 = 0X0000; /* <<< 0: no wait for remote requeset */
TRTRR0 = 0X0000; /* <<< 0: Data / 1: Remote frame Trx */
BVALR0 = 0X000F; /* message buffer are valid */
FLAG_CAN_BEGIN = 1;
FLAG_CAN_STOP = 0;
} |
