//
//
//
//-------------------------------------------------------------------------------
// FILENAME : alu.v
// DESCRIPTION : Component was generated by Alatek HDL Wizard
// Details :
// Arithmetic Logic Unit
// Width: 8
// Unit type - arith.
// All outputs are registered by CLK signal
// Clock (CLK ) signal is edge sensitive
// Clear (CLR ) is active : high
// Clear signal is asynchronous
// Clock enable (CE ) is active: high
// Carry in (CI ) active: high
// Carry out (CO ) active: high
// Overrflow (OV ) active: high
//
// CREATED : 2006-1-13, 14:24:8
// VERSION : 2.0
//-------------------------------------------------------------------------------
module alu (A ,B ,S ,CI ,CLK ,CLR ,CE ,CO ,OV ,Q );
input [7:0] A ;
input [7:0] B ;
input [2:0] S ;
input CI ;
input CLK ;
input CLR ;
input CE ;
output CO ;
output OV ;
output [7:0] Q ;
reg CO ;
reg OV ;
reg [7:0] Q ;
reg [7:0] RESULT2;
reg CO_OUT ;
reg OV_OUT ;
`define ADD_M 3'b000
`define SUB_M 3'b001
`define ADD_CIN 3'b010
`define SUB_CIN 3'b011
`define INC_A 3'b100
`define DEC_A 3'b101
`define INC_B 3'b110
`define DEC_B 3'b111
reg C_TEMP;
reg CO_TEMP ;
reg [7:0] A_TEMP ;
reg [7:0] B_TEMP ;
reg [7:0] TEMP_R;
always @(A or B or CI or S )
begin
A_TEMP = 0;
B_TEMP = 0;
TEMP_R = 0;
case (S )
`ADD_M : begin
A_TEMP = {1'b0,A [6:0]};
B_TEMP = {1'b0,B [6:0]};
end
`SUB_M : begin
A_TEMP = {1'b0,A [6:0]};
B_TEMP = {1'b0,B [6:0]};
end
`ADD_CIN : begin
A_TEMP = {1'b0,A [6:0]};
B_TEMP = 0;
end
`SUB_CIN : begin
A_TEMP = {1'b0,A [6:0]};
B_TEMP = 0;
end
`INC_A : begin
A_TEMP = {1'b0,A [6:0]};
B_TEMP = 0;
end
`DEC_A : begin
A_TEMP = {1'b0,A [6:0]};
B_TEMP = 0;
end
`INC_B : begin
A_TEMP = {1'b0,B [6:0]};
B_TEMP = 0;
end
`DEC_B : begin
A_TEMP = {1'b0,B [6:0]};
B_TEMP = 0;
end
default : begin
A_TEMP = 0;
B_TEMP = 0;
end
endcase
case (S )
`SUB_M , `SUB_CIN , `DEC_A , `DEC_B : begin
case (S )
`SUB_M , `SUB_CIN : TEMP_R = A_TEMP - B_TEMP - CI ;
default : TEMP_R = A_TEMP - 1;
endcase
CO_TEMP = ((~A [7]) & B [7]) | (TEMP_R[7] & ((~A [7]) | B [7]));
end
`ADD_M , `ADD_CIN , `INC_A , `INC_B : begin
case (S )
`ADD_M , `ADD_CIN : TEMP_R = A_TEMP + B_TEMP + CI ;
default : TEMP_R = A_TEMP + 1;
endcase
CO_TEMP = (A [7] && B [7]) | (TEMP_R[7] & (A [7] | B [7]));
end
default : begin
TEMP_R = 0;
CO_TEMP = 1'b0;
end
endcase
if ((S == `ADD_M) || (S == `SUB_M))
C_TEMP = A [7] ^ B [7];
else
C_TEMP = A [7];
RESULT2 = {(C_TEMP ^ TEMP_R[7]),TEMP_R[6:0]};
CO_OUT = CO_TEMP ;
OV_OUT = CO_TEMP ^ TEMP_R[7];
end
always @(posedge CLK or posedge CLR )
begin
if (CLR == 1'b1) begin
CO = 1'b0;
OV = 1'b0;
Q = 8'b00000000;
end else if (CE == 1'b1) begin
Q = RESULT2;
CO = CO_OUT ;
OV = OV_OUT ;
end
end
endmodule |
