Xilinx Virtex-6 HXT&n

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苹果也疯狂发表于 2014-5-25 17:52 | 只看该作者

Xilinx Virtex-6 HXT&n

连接器, 收发器, 带宽, 技术, 通道

本卡采用Xilinx Virtex-6 HX565Tor HX380T FPGA（40 GTX（6.6Gbps）和24（11.13Gbps） GTH串行收发器）技术，提供8个通道的PCI Express Gen 2，四个SFP+连接器（40 Gbps），MoSys的带宽引擎®IC（576MB的多组1T-SRAM，带有串行10G接口和板载ALU），高达16 GB的DDR3 SO-DIMM，QDR II，10个11.18 Gbps和10个6.6Gbps串行端口。板上FPGA夹层连接器（FMC）连同现成的固定-移动的融合模块，连接各种不同的功能板用于各种不同应用程序。

Powered by Xilinx Virtex-6 HX565Tor HX380T FPGA (with 40 GTX (6.6Gbps) & 24 GTH (11.13Gbps) serial transceivers), this optical network card provides access to eight lanes of PCI Express Gen 2 , four SFP+ connectors (40 Gbps), MoSys Bandwidth Engine® IC (576Mb Multibank 1T-SRAM with Serial 10G Interface and onboard ALU), up to 16 GB of DDR3 SO-DIMM, QDR II, ten 11.18 Gbps
and ten 6.6Gbps serial ports. The on-board FPGA Mezzanine Connectors (FMC) along with off-the-shelf FMC modules, expend the functionality of the board for variety of different applications.

Two SFP+ ports are powered by an external PHY chip (with Electrical Dispersion Compensation) supporting short range, medium range, and long range optical interfaces. Two additional SFP+ ports are connected directly to the GTH transceivers of the on-bo ard FPGA.

Features:
▪ Xilinx Virtex-6 HX380T or HX565T FPGA
▪ x8 PCI Express Gen2 Edge Connector
▪ x2 SFP+ ports with Electrical Dispersion Compensation (EDC) & CDR support through external PHY chips (ideal for Long Range applications)
▪ x2 SFP+ ports with direct interfaces to the on-board
FPGA's GTH (10G) serial transceivers (ideal for Short Range applications)
▪ MoSys Bandwidth Engine® IC (576Mb Multibank 1T-SRAM with Serial 10G Interface and onboard ALU)
▪ x2 DDR-3 SO-DIMM (up to 16GB)
▪ x2 QDR-II Components (each 4Mx18)
▪ x2 FPGA Mezzanine Connectors (FMC)

- FMC #1: 9 LVDS I/Os and 10 GTH (11.18 Gbps) Serial Transceivers

- FMC # 2: 34 LVDS I/Os and 10 GTX (6.6 Gbps) Serial Transceivers
▪ Configuration through JTAG or CPLD
▪
USB to UART
▪
ATX and DC power supplies for
PCI Express
and
Stand Alone
operations
▪
LEDs & Pushbuttons
▪ Size: 9.5" x 4.0"
►Software:

[url=]-[/url] PCI Express Driver Source Code (C) - Windows XP or Linux

- PCI Express Back End (High Performance DMA Engine)
►Kit Content:
- HTG-V6HXT-X8PCIE Board
- Hardware Setup Guide
- CD ROM with User Manual, Schematics (in searchable pdf format) , Software Drivers (eval.), PCI Express Gen 2 CoreGen PIO design , ChipScope PRO IBERT reference/test designs, Xilinx MIG based DDR3 and QDRII memory controllers
►Ordering information
Part Numbers:

-HTG-V6HXT-X8PCIE-380-2
(populated with XC6VHX380T-2FFG1923 FPGA)
-HTG-V6HXT-X8PCIE-380-3
(populated with XC6VHX380T-3FFG1923 FPGA)
-HTG-V6HXT-X8PCIE-565 (populated with XC6VHX565T-2FFG1923 FPGA)Reference Designs:
Extensible FPGA Framework (EFW) provides a verified set of productivity solutions, including module targeted physical interface components, device drivers and APIs for the HTG-V6HXT-X16PCIE platform. The EFW enables end user to skip the tedious and time consuming phase of the platform's bring-up by providing targeted and hardware verified physical interfaces.
Additionally, the framework allows users to simulate, integrate and test Ethernet and DMA cores (licensed separately) in their designs with time limited synthesizable binaries and simulation libraries.
Following figure shows the elements and interfaces of the framework.

The base framework provides all the design files, device drivers and API to access the memory mapped registers inside the FPGA. It enables an end user to instantiate and control custom logic blocks through the GUI application.
Another key feature of the base EFW is the capability to program and erase the G18 BPI memory on the HTG-V6H-x8PCIE through the PCIe interface at very high speeds. Integrating the Field Upgradable
controller allows any user design to be field upgradeable through PCIe. It can also eliminate the need for the USB platform cable during the design and development phase.
The base framework also provides the targeted (MIG generated) wrapper for the 1066Mbps (533MHz) DDR3 and 350MHz QDRII+ controllers. Memory mapped MDIO and I2C controllers are also integrated in the EFW to control and configure the PHYs and clock elements on HTG-V6H-x8PCIE module.
EFW also serves as the evaluation platform for the 10G low latency and dual-mode 10G/1G Ethernet IP solutions. It allows the user to test the 1G and 10G Ethernet interface capabilities of the HTG-V6H-x8PCIE without any code development. User can then extend the Ethernet interfaces to user specific designs through the industry standard AXI4-Streaming interface. Full simulation libraries included in the EFW enables the user to simulate and test the Ethernet interfaces before licensing the solutions.
EFW’s integrated (time limited) 4-channel 128-bit data path (@ 250MHz) block DMA controller along with the PCIe device drivers allows the user to implement and verify high speed data and packet applications on the HTG-V6H-x8PCIE module.
Key Features
·
Framework includes module targeted
and hardware verified RTL blocks for:
o
x8 PCIe Gen2 hard IP block with PCIe application interface and arbiter
o
AXI4-Lite master/arbiter for distributed control and configuration of various EFW blocks
o
Two 1066Mbps/533MHz DDR3 controllers
o
Two 350 MHz QDRII+ controllers
o
Field upgradeable flash (FUp) controller for in-system field upgrade of the FPGA image through PCIe interface
o
MDIO and I2C controllers
o
DRP controller for run-time control and configuration of the GTH Transcievers
·
Time limited (30min) synthesizable binaries and full simulation libraries for hardware verified Ethernet solutions up to 10Gbps:
o
10Gbps Low Latency Ethernet
using the SFP+ interface on the module
o
Dual Mode 10G/1G Ethernet
using the SFP+ interface on the module
·
Time limited (30min) synthesizable binaries and full simulation libraries for  hardware verifiedMulti-channel (4) 128-bit data path scatter-gather block DMA controller
·
All modules with industry standard AXI-4 streaming interface for data path and AXI-4 Lite interface for control, configuration and memory interface
·
Top level RTL interface wrapper for custom user design block for easy implementation of user logic
·
Linux device drivers and API for PCIe interface
·
A single unified GUI for entire EFW with scripting support

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