LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY jiaotd IS
PORT(CLK,RST:IN BIT;
S:IN BIT;
TMGH,TMGL,TMY1,TCGH,TCGL,TCY1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
MR,MY,MG,CR,CY,CG:OUT BIT);
END jiaotd;
ARCHITECTURE ONE OF jiaotd IS
TYPE state IS(MGCR,MYCR,MRCG,MRCY);
SIGNAL current_state,next_state:state;
BEGIN
--REG ROCESS(RST,CLK)
--BEGIN
--IF RST='1'THEN current_state<=MGCR;
--ELSIF CLK'EVENT AND CLK='1'THEN
--current_state<=next_state;
--END IF;
--END PROCESS;
COMROCESS(current_state,S,CLK)
VARIABLE Q1,Q2,Q3,Q4 :STD_LOGIC;
VARIABLE TMG :STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE TMY :STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE TCG :STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE TCY :STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF RST='1'THEN current_state<=MGCR;
ELSIF CLK'EVENT AND CLK='1'THEN
current_state<=next_state;
END IF;
CASE current_state IS
WHEN MGCR => MR<='0';MY<='0';MG<='1';CR<='1';CY<='0';CG<='0';
IF S='1' AND Q1='0' THEN next_state<=MYCR;
ELSIF S='0' AND Q1='1'THEN TMG:=TMG-1;
ELSIF S='0'AND Q1='0'THEN TMG:="00010000";
ELSIF TMG=1 THEN TMG:="01100000";Q1:='0';
ELSIF TMG(3 DOWNTO 0)="0000" THEN TMG(3 DOWNTO 0):="1001";TMG:=TMG-1;
ELSE TMG:=TMG-1;Q1:='1';next_state<=MGCR;
END IF;
WHEN MYCR => MR<='0';MY<='1';MG<='0';CR<='1';CY<='0';CG<='0';
IF Q2='0' THEN next_state<=MRCG;
ELSIF TMY="0001"THEN TMY:="0011";Q2:='0';
ELSE TMY:=TMY-1;Q2:='1';next_state<=MYCR;
END IF;
WHEN MRCG => MR<='1';MY<='0';MG<='0';CR<='0';CY<='0';CG<='1';
IF S='0'OR Q3='0' THEN next_state<=MRCY;
ELSIF TCG=1 THEN TCG:="00100000";Q3:='0';
ELSE TCG:=TCG-1;Q3:='1';next_state<=MYCR;
END IF;
WHEN MRCY => MR<='1';MY<='0';MG<='0';CR<='0';CY<='0';CG<='1';
IF Q4='0' THEN next_state<=MRCG;
ELSIF TCY="0001"THEN TCY:="0011";Q4:='0';
ELSE TCY:=TCY-1;Q4:='1';next_state<=MYCR;
END IF;
END CASE;
TMGH<=TMG(7 DOWNTO 4);
TMGL<=TMG(3 DOWNTO 0);
TMY1<=TMY;
TCY1<=TCY;
TCGH<=TCG(7 DOWNTO 4);
TCGL<=TCG(3 DOWNTO 0);
END PROCESS;
END ONE;
状态之间不转换，时序也好像有问题，请高人指点一下 |
