我写了一段双边沿计数器，高手帮我找找错误吧，仿真时无输出信号： `timescale 1ns/1ns
module test_cunt() ;
reg clk,rst;
reg a,b;
wire [1:0] a_reg,b_reg,snd_state;
wire a_snd,b_snd;
wire [7:0] sum,sum_reg; initial
begin
rst = 'b0 ;
clk = 'b0 ;
#10 rst = 'b1 ;
clk = 'b1 ;
forever #5 clk = ~clk ;
end initial
begin
a = 'b0;
forever #12 a=~a;
end initial
begin
b = 'b0;
forever #7 b=~b;
end cunt test_cunt(.rst(rst), .clk(clk), .a(a), .b(b),
.sum(sum),.sum_reg(sum_reg),
.snd_state(snd_state),.a_snd(a_snd),.b_snd(b_snd),
.a_reg(a_reg),.b_reg(b_reg));
//.snd_state(snd_state),.a_snd(a_snd),.b_snd(b_snd),.sum_reg(sum_reg)); endmodule | 
