用原理图画了个电路，在综合时候出现下面错误，我得clr是输入信号啊 ，为什么有下面的错误呢，Net 'clr'cannot be connected both to an input port and an instance output pin.
网上查了下，解决方法1，Before a schematic design is implemented, it is first converted to either Verilog or VHDL (depending on the setting of the Generated Simulation Language property). As part of the conversion process, a Design Rule Check (DRC) will be run on the selected schematic and any underlying schematics. "Error: DesignEntry:222" indicates that an I/O Marker with an Input Port polarity is connected to an output pin of one of the symbol instances in the schematic drawing. This is not allowed, as it would create an electrical source conflict. 但我的‘clk没接输出啊，请高手指教
附原理图 | 
