实验 9
全加器// 1 bit full adder
1 位全加器
module full_add(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign {cout,sum}=a+b+cin;
endmodule
附录：各种不同的描述方式实现的1位全加器
1，调用门元件实现的1 位全加器
module full_add1(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire s1,m1,m2,m3;
and (m1,a,b),
(m2,b,cin),
(m3,a,cin);
xor (s1,a,b),
(sum,s1,cin);
or (cout,m1,m2,m3);
endmodule
2 数据流描述的1 位全加器
module full_add2(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum = a ^ b ^ cin;
assign cout = (a & b)|(b & cin)|(cin & a);
endmodule
3 行为描述的1 位全加器
module full_add4(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg sum,cout; //在always 块中被赋值的变量应定义为reg 型
reg m1,m2,m3;
always @(a or b or cin)
begin
sum = (a ^ b) ^ cin;
m1 = a & b;
m2 = b & cin;
m3 = a & cin;
cout = (m1|m2)|m3;
end
endmodule
4 混合描述的1 位全加器
module full_add5(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg cout,m1,m2,m3; //在always 块中被赋值的变量应定义为reg 型
wire s1;
xor x1(s1,a,b); //调用门元件
always @(a or b or cin) //always 块语句
begin
m1 = a & b;
m2 = b & cin;
m3 = a & cin;
cout = (m1| m2) | m3;
end
assign sum = s1 ^ cin; //assign 持续赋值语句
endmodule
实验 10
半减器
module half_sub(diff,sub_out,x,y);
output diff,sub_out;
input x,y;
reg diff,sub_out;
//行为描述
always@(x or y)
case ({x,y})
2'b00 : begin diff= 0; sub_out = 0;end
2'b01 : begin diff= 1; sub_out = 1;end
2'b10 : begin diff= 1; sub_out = 0;end
2'b11 : begin diff= 0; sub_out = 0;end
default: begin diff= x; sub_out =x;end
endcase
endmodule
实验 11
全减器
module full_sub(diff,sub_out,x,y,sub_in);
output diff,sub_out;
input x,y,sub_in;
reg diff,sub_out;
//行为描述
always@(x or y or sub_in)
case ({x,y,sub_in})
3'b000 : begin diff= 0; sub_out = 0;end
3'b001 : begin diff= 1; sub_out = 1;end
3'b010 : begin diff= 1; sub_out = 1;end
3'b011 : begin diff= 0; sub_out = 1;end
3'b100 : begin diff= 1; sub_out = 0;end
3'b101 : begin diff= 0; sub_out = 0;end
3'b110 : begin diff= 0; sub_out = 0;end
3'b111 : begin diff= 1; sub_out = 1;end
default: begin diff= x; sub_out =x;end
endcase
endmodule |
