网上找到的 8位乘法器，移位加法器实现 的 VHDL代码 不知道移位加法器是什么东西？我看这个程序看了好久也没有感觉出来！ library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity multi8x8 is
port(clk, start: in std_logic;
a, b: in std_logic_vector(7 downto 0);
ariend: out std_logic;
dout: out std_logic_vector(15 downto 0));
end entity; architecture a of multi8x8 is
component arictl is
port(clk, start: in std_logic;
ariend, restall, clkout: out std_logic);
end component;
component andarith is
port(din: in std_logic_vector(7 downto 0);
abin: in std_logic;
dout: out std_logic_vector(7 downto 0));
end component;
component sreg8b is
port(clk, load: in std_logic;
din: in std_logic_vector(7 downto 0);
qb: out std_logic);
end component;
component reg16b is
port(clk, clr: in std_logic;
d: in std_logic_vector(8 downto 0);
q: out std_logic_vector(15 downto 0));
end component;
component adder8b is
port(cin: in std_logic;
a, b: in std_logic_vector(7 downto 0);
s: out std_logic_vector(7 downto 0);
cout: out std_logic);
end component;
signal s1, s2, s3, s4: std_logic;
signal s5: std_logic_vector(7 downto 0);
signal s6: std_logic_vector(8 downto 0);
signal s7: std_logic_vector(15 downto 0);
begin
dout<=s7; s1<='0';
u1: arictl
port map(clk=>clk, start=>start, clkout=>s2, restall=>s3, ariend=>ariend);
u2: sreg8b
port map(clk=>s3, load=>s2, din=>a, qb=>s4);
u3: andarith
port map(abin=>s4, din=>b, dout=>s5);
u4: adder8b
port map(cin=>s1, a=>s7(15 downto 8), b=>s5, s=>s6(7 downto 0), cout=>s6(8));
u5: reg16b
port map(clk=>s2, clr=>s3, d=>s6, q=>s7);
dout<=s7; s1<='0';
end architecture;
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity arictl is
port(clk, start: in std_logic;
ariend, clkout, restall: out std_logic);
end entity; architecture a of arictl is
signal count: std_logic_vector(3 downto 0);
begin
restall<=start;
process(clk, start)is
begin
if start='1' then count<="0000";
elsif (clk'event and clk='1') then
if count<8 then
count<=count+'1';
end if;
end if;
end process;
process(clk, count, start)is
begin
if start='0' then
if count<8 then
clkout<=clk;
ariend<='0';
else
clkout<=clk;
ariend<='1';
end if;
end if;
end process;
end architecture;
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sreg8b is
port(clk, load: in std_logic;
din: in std_logic_vector(7 downto 0);
qb: out std_logic);
end entity; architecture a of sreg8b is
signal temp: std_logic_vector(7 downto 0);
begin
process(clk, load) is
begin
if(clk'event and clk='1')then
if load='1' then
temp<=din;
else
temp(6 downto 0)<=temp(7 downto 1);
end if;
end if;
end process;
qb<=temp(0);
end architecture; ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity andarith is
port(din: in std_logic_vector(7 downto 0);
abin: in std_logic;
dout: out std_logic_vector(7 downto 0));
end entity; architecture a of andarith is
begin
process(abin, din)
begin
for i in 0 to 7 loop
dout(i)<=din(i) and abin;
end loop;
end process;
end architecture;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg16b is
port(clk, clr: in std_logic;
d: in std_logic_vector(8 downto 0);
q: out std_logic_vector(15 downto 0));
end entity; architecture a of reg16b is
signal r16s: std_logic_vector(15 downto 0);
begin
process(clk, clr) is
begin
if clr='1' then r16s<="0000000000000000";
elsif(clk'event and clk='1') then
r16s(6 downto 0)<=r16s(7 downto 1);
r16s(15 downto 7)<=d;
end if;
end process;
q<=r16s;
end architecture;
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity adder8b is
port(cin: in std_logic;
a, b: in std_logic_vector(7 downto 0);
s: out std_logic_vector(7 downto 0);
cout: out std_logic);
end entity; architecture art of adder8b is
component adder4b is
port(c4: in std_logic;
a4, b4: in std_logic_vector(3 downto 0);
s4: out std_logic_vector(3 downto 0);
co4: out std_logic);
end component;
signal sc: std_logic;
begin
u1: adder4b
port map(c4=>cin, a4=>a(3 downto 0), b4=>b(3 downto 0),
s4=>s(3 downto 0), co4=>sc);
u2: adder4b
port map(c4=>sc, a4=>a(7 downto 4), b4=>b(7 downto 4),
s4=>s(7 downto 4), co4=>cout);
end architecture;
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder4b is
port(c4: in std_logic;
a4, b4: in std_logic_vector(3 downto 0);
s4: out std_logic_vector(3 downto 0);
co4: out std_logic);
end entity; architecture art of adder4b is
signal s5: std_logic_vector(4 downto 0);
signal a5, b5: std_logic_vector(4 downto 0);
begin
a5<='0'&a4;
b5<='0'&b4;
s5<=a5+b5+c4;
s4<=s5(3 downto 0);
co4<=s5(4);
end architecture; | 
