you may use The parallel boot mode that uses a boot table mapped into ext data space, i.e.
0x4000-FFFF. To
get the address of the table it first reads I/O space at 0xFFFF, and if
unsuccessful,
reads Data space at 0xFFFF and 0xFFFE. It's looking for an address which
contains the
boot table "signature" 0x10AA or 0x08AA. Check out SPRA618 if you haven't yet.
So the answer is you have to have a boot vector at 0xFFFE-FFFF in Data or I/O
space which
points to your boot table. Easiest thing with a single ROM/Flash is just make
sure it
covers addresses 0xFFFE/FFFF. For example a 32K x 8 mapped at 0x8000-FFFF could
contain
the boot vector, the boot table, and code to load at boot time.
Of course TI with their infinite wisdom decides that boot vector and table
should reside
in data space, while the loadable code is in program space! So either you map
the flash
to both and cut into the space you'd like to put RAM, or you use a GPIO or some
other
method to switch the _DS / _PS lines after boot. In other words: at boot time,
your flash
exists in data and program space (so it can read the boot stuff and code)
leaving ext RAM
unmapped; after boot you set the bit so the flash exists in program space only
and RAM is
in data space. You pretty much get the impression TI never tried to use
parallel boot
mode...
Or you skip this nonsense, disable TI's ROM while mumbling a few obscenities,
then write
your own loader
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