//MAIN CORE
//*********************
//Sequential logic style
always@(posedge clk_* or negedge rest_n)
begin : SEQ_BLOCK_NAME
if(rst_n==1’b0)
counter<=4’b0;
else
begin
if (expression)
counter <= #`DLY siginal_b;
else;
end
end // SEQ_BLOCK_NAME
//Combinational logic style
always@(signal_a or signal_b)
begin:COM_BLOCK-NAME
case (expression)
item1 :begin
signal_c=*****;
end
item2 : //statement;
default ://statement;
endcase
end // COM_BLOCK_NAME
//*********************
endmodule
MACRO DEFINE TEMPLATE
//********************************************************
//
// Copyright(c)2005, Hisilicon Technologies Co., Ltd
// All rights reserved
//
// IPLIB INDEX : IP lib index just as UTOPIA_B
// IPName : the top module_name of this ip, usually, issame as
the small ipclassified name just as UTOPIA
// File name : macro.v
// Module name :
// Full name : complete English name of the abbreviatedmodule_name
// Author : Author
// Email : Author’s email
// Data : 2005/07/20
// Version : current version, just this: v1.0, must sameas the CVS version
//
// Abstract :
//
// Called by : Father module .
//
// Modification history
// ----------------------------------------------------------------------------
// Version Data(yyyy/mm/dd) name
// Description
//
// $Log$
//
//*************************************************************
//*******************
//DEFINE(s)
//*******************
`define UDLY 1 //Unit delay, for non_blocking assignmentsin sequential logic
`define DATA_WIDTH 32 //AHB data width
`define ADDR_WIDTH 32 //AHB address width |
