FIFO — Result Register FIFO Mode
If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on.
If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or end of a conversion sequence; conversion results are placed in consecutive result registers between sequences. The result register counter wraps around when it reaches the end of the result register file. The conversion counter value in ATDSTAT0 can be used to determine where in the result register file, the current conversion result will be placed.
1 = Conversion results are placed in consecutive result registers (wrap around at end).
0 = Conversion results are placed in the corresponding result register up to the selected sequence
length.
英文说明了，如果是非FIFO模式，那么转换的结果按照顺序从头开始存放；
如果是FIFO模式，那么就不一定从头开始，存放的结果如果存到了寄存器末端，就会转到开头去存。
简单点说就是一个定义了长度了从开头开始存放，而一个从当前位置开始，不够存再掉头，形成loop
看下面一段英文，在一次转换序列完成时SCF是置位的，直到有三个条件中的某一个出现会清除
SCF — Sequence Complete Flag
This flag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN=1), the flag is set after each one is completed. This flag is cleared when one of the
following occurs:
A) Write “1” to SCF
B) Write to ATDCTL5 (a new conversion sequence is started)
C) If AFFC=1 and read of a result register
[此贴子已经被作者于2005-4-15 17:48:35编辑过]
[此贴子已经被作者于2005-4-15 17:51:11编辑过] | 
